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| Functional Description |
R |
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Table 16. Data Rate Control Bits |
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AGPCNTL | AGPCMD. | AGPCMD. | AGPCMD. | AGPCMD. | MCH =>AGP Master Write |
.FWCE | FWPE | DRATE | DRATE | DRATE | Protocol |
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| [bit 2] | [bit 1] | [bit 0] |
|
0 | 0 | X | X | X | 1x |
1 | 1 | 0 | 0 | 1 | 1x |
1 | 1 | 0 | 1 | 0 | 2x strobing |
1 | 1 | 1 | 0 | 0 | 4x strobing |
5.3.6AGP FRAME# Transactions on AGP
The MCH accepts and generates AGP FRAME# transactions on the AGP bus. The MCH guarantees that AGP FRAME# accesses to system memory are kept coherent with the processor caches by generating snoops to the host bus. LOCK#, SERR#, and PERR# signals are not supported.
MCH Initiator and Target Operations
Table 17 summarizes MCH target operation for AGP FRAME# initiators. The cycles can be either destined to system memory or the hub interface.
Table 17. PCI Commands Supported by the Intel® MCH (When Acting as a FRAME# Target)
PCI Command | C/BE[3:0]# | Intel® MCH | |
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| Encoding | Cycle Destination | Response as a FRAME# |
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| Target |
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Interrupt Acknowledge | 0000 | N/A | No response |
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Special cycle | 0001 | N/A | No response |
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I/O Read | 0010 | N/A | No response |
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I/O Write | 0011 | N/A | No response |
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Reserved | 0100 | N/A | No response |
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Reserved | 0101 | N/A | No response |
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Memory Read | 0110 | System memory | Read |
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| 0110 | Hub interface | No response |
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Memory Write | 0111 | System memory | Posts data |
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| 0111 | Hub interface | No response |
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Reserved | 1000 | N/A | No response |
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Reserved | 1001 | N/A | No response |
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Configuration Read | 1010 | N/A | No response |
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Configuration Write | 1011 | N/A | No response |
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Memory Read Multiple | 1100 | System memory | Read |
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| 1100 | Hub interface | No response |
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Intel® 82845 MCH for SDR Datasheet | 115 |
