SMLT1-Secondary Master Latency Timer Register Device | Intel 845

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		3.6.11	SBUSN1—Secondary Bus Number Register (Device 1)		86
		3.6.12	SUBUSN1—Subordinate Bus Number Register (Device 1)		86
		3.6.13	SMLT1—Secondary Master Latency Timer Register (Device 1)		87
		3.6.14	IOBASE1—I/O Base Address Register (Device 1)		88
		3.6.15	IOLIMIT1—I/O Limit Address Register (Device 1)		88
		3.6.16	SSTS1—SecondaryPCI-PCI Status Register (Device 1)		89
		3.6.17	MBASE1—Memory Base Address Register (Device 1)		90
		3.6.18	MLIMIT1—Memory Limit Address Register (Device 1)		90
		3.6.19	PMBASE1—Prefetchable Memory Base Address
			Register (Device 1)		91
		3.6.20	PMLIMIT1—Prefetchable Memory Limit Address
			Register (Device 1)		91
		3.6.21	BCTRL1—PCI-PCI Bridge Control Register (Device 1)		92
		3.6.22	ERRCMD1—Error Command Register (Device 1)		93
		3.6.23	DWTC—DRAM Write Thermal Management Control
			Register (Device 1)		94
		3.6.24	DRTC—DRAM Read Thermal Management Control
			Register (Device 1)		95
4	System Address Map				97
	4.1	Memory Address Ranges			97
		4.1.1	VGA and MDA Memory Space		99
		4.1.2	PAM Memory Spaces		100
		4.1.3	ISA Hole Memory Space		100
		4.1.4	TSEG SMM Memory Space		101
		4.1.5	IOAPIC Memory Space		101
		4.1.6	System Bus Interrupt APIC Memory Space		101
		4.1.7	High SMM Memory Space		101
		4.1.8	AGP Aperture Space (Device 0 BAR)		102
		4.1.9	AGP Memory and Prefetchable Memory		102
		4.1.10	Hub Interface Subtractive Decode		102
	4.2	AGP Memory Address Ranges			102
		4.2.1	AGP DRAM Graphics Aperture		103
	4.3	System Management Mode (SMM) Memory Range			103
		4.3.1	SMM Space Definition		104
		4.3.2	SMM Space Restrictions		104
	4.4	I/O Address Space			105
	4.5	Intel® MCH Decode Rules and Cross-Bridge Address Mapping			105
		4.5.1	Hub Interface Decode Rules		105
		4.5.2	AGP Interface Decode Rules		106
5	Functional Description				107
	5.1	System Bus			107
		5.1.1	Dynamic Bus Inversion		107
		5.1.2	System Bus Interrupt Delivery		108
		5.1.3	Upstream Interrupt Messages		108
	5.2	System Memory Interface			109
		5.2.1	Single Data Rate (SDR) SDRAM Interface Overview		109
		5.2.2	Memory Organization and Configuration		109
			5.2.2.1	Configuration Mechanism For DIMMs	110
		5.2.3	Memory Address Translation and Decoding		111
		5.2.4	DRAM Performance Description		112
			5.2.4.1	Data Integrity (ECC)	112
Intel® 82845 MCH for SDR Datasheet					5

Image 5

Intel 845 SMLT1-Secondary Master Latency Timer Register Device, PMBASE1-Prefetchable Memory Base Address, 100, 101, 102

Contents

Document Number Intel 845 Chipset 82845 Memory Controller Hub MCH for SDR Intel 82845 MCH for SDR Datasheet Contents Register Device System Management Mode SMM Memory Range 103 SMLT1-Secondary Master Latency Timer Register DevicePMBASE1-Prefetchable Memory Base Address PMLIMIT1-Prefetchable Memory Limit Address 115 114117 118 Tables Revision Description Date Revision History Intel 82845 MCH Features System Block Diagram Term Description Terminology and NotationsGeneral Terminology Number Format Notation Data Type NotationData Type Size Number Format Notation Example Document Reference Documents Intel 82845 MCH Overview Intel 845 Chipset System Architecture System Bus Interface System Bus Error Checking AGP Interface System Memory InterfaceMemory Capacity Technology SDR PC133 Intel MCH Clocking Hub InterfaceIntel MCH Clock Ratio Table Interface Speed Processor Bclk System Interrupts Powerdown Flow Signal Description Intel MCH Simplified Block Diagram Signal Name Type Description System Bus SignalsDBIx# Data Bits Strobe Address Bits RS20 Response Type Strobe Data Bits Sdram Column Address Strobe SCAS# is used with SRAS# SDR Sdram Interface SignalsHub Interface Signals AGP Addressing Signals AGP Interface SignalsDuring SBA Operation Not Used During FRAME# Operation Not Used AGP Status Signals AGP Flow Control SignalsRBF# WBF# 5 AGP/PCI Signals AGP Strobes Signals Parity Command/Byte Enable Bclk Clocks, Reset, and Miscellaneous SignalsBCLK# Cmos RSTIN# System Memory Rcomp Voltage Reference and Power SignalsAGTL+ Bus Termination Voltage Inputs These pins provide Signal Name Reset States During ResetState System Bus Interface Register Terminology Register Description MCH Function Bus 0, Device # PCI Bus Configuration Space AccessIntel MCH Internal Device Assignments Routing Configuration Accesses Standard PCI Bus Configuration Mechanism I/O Mapped Registers CONFADDR-Configuration Address Register Bit Descriptions Configuration Enable Cfge Address 0CFCh Default Value 00000000h Access Size Bits CONFDATA-Configuration Data RegisterMemory-Mapped Register Space Memory-mapped Register Address Map Row Parameters SDR Clocks Affected Address Offset 2Ch Default Value 00h Access Size BitsDRAMWIDTH-DRAM Width Register DQCMDSTR-Strength Control Register SDQ and CMD Signal Groups Memory Address Offset 31h Default Value 00h Access Size Bits CKESTR-Strength Control Register Scke Signal Group Memory Address Offset 32h Default Value 00h Access Size Bits CSBSTR-Strength Control Register SCS# Signal Group Memory Address Offset 33h Default Value 00h Access Size Bits CKSTR-Strength Control Register Clock Signal Group Memory Address Offset 34h Default Value 00h Access Size Bits RCVENSTR-Strength Control Register Rcvenout Signal Group Address Register Register Name Default Access Intel MCH Configuration Space DeviceHost-Hub Interface Bridge Device Registers Device Value Fdhc EAPSmram Esmramc DID-Device Identification Register Device VID-Vendor Identification Register DeviceBit Description Bit Description Address Offset 04-05h Default 0006h Access Size Bits PCICMD-PCI Command Register Device Size Bits Address Offset 06-07h Default Value 0090h AccessPCISTS-PCI Status Register Device Address Offset 0Bh Default Value 06h Access Size Bits Address Offset 0Ah Default Value 00h Access Size BitsRID-Revision Identification Register Device SUBC-Sub-Class Code Register Device Address Offset 0Dh Default Value 00h Access Size Bits MLT-Master Latency Timer Register DeviceAddress Offset 0Eh Default 00h Access Size Bits Bit Description Hardwired to 00h. Writes have no effect Offset 10-13h Default 00000008h Access Size Bits APBASE-Aperture Base Configuration Register Device CAPPTR-Capabilities Pointer Device SVID-Subsystem Vendor Identification DeviceSID-Subsystem Identification Device Address Offset 51h Default Value 00h Access Size Bits AGPM-AGP Miscellaneous Configuration Register DeviceOffset 60-67h DRB0-DRB7 Default 00h Access Size Bits 15 DRB07-DRAM Row Boundary Registers Device DRA-DRAM Row Attribute Registers Device Offset 70-73h DRA0-DRA3 Default 00h Access Size Bits Corresponding row DRT-DRAM Timing Register Device Offset 78-7Bh Default 00000010h Access Size Bits Offset 7C-7Fh Default 00000000h Access Size Bits DRC-DRAM Controller Mode Register Device = Normal operation Address Offset 86h Default Value 00h Access Size Bits DERRSYN-DRAM Error Syndrome Register DeviceEAP-Error Address Pointer Register Device Bits 7 Bits 6 Bits 5 Bits 4 Description 21 PAM06-Programmable Attribute Map Registers Device PAM6 PAM5 PAM4 PAM3 PAM2 PAM1 PAM0 PAM Register Attributes PAM Reg Attribute Bits Memory Segment Comments Offset DOS Application Area 00000h-9FFFh FDHC-Fixed Dram Hole Control Register Device Address Offset 97h Default Value 00h Access Size Bits SMRAM-System Management RAM Control Register Device Global Smram Enable GSMRAME-R/W/L SMRAML1EN SML1-RO. Hardwired to SMRAMCache SMCACHE-RO. Hardwired toSMRAML2EN SML2-RO. Hardwired to ESMRAMC-Extended System Mgmt RAM Control Register Device ACAPID-AGP Capability Identifier Register Device This register reports AGP device capability/status AGPSTAT-AGP Status Register Device SideBand Address Enable Sbaen AGPCMD-AGP Command Register DeviceAGP Enable Agpen Fast Write Enable Fwen Data Rate 4x Override AGPCTRL-AGP Control Register Device Aperture Size Address Offset B4h Default Value 00h Access Size BitsAPSIZE-Aperture Size Device ATTBASE-Aperture Translation Table Base Register Device Address Offset BCh Default Value 00h Access Size Bits AMTT-AGP Interface Multi-Transaction Timer Register Device Address Offset BDh Default Value 00h Access Size Bits LPTT-AGP Low Priority Transaction Timer Register Device TOM-Top of Low Memory Register Device Address Offset C4-C5h Default Value 0100h Access Size Bits Apic Memory Range Disable APICDIS-R/W MCHCFG-MCH Configuration Register DeviceOffset C6-C7h Default 0000h Access Size Bits Address Offset C8-C9h Default Value 0000h Access Size Bits ERRSTS-Error Status Register Device Address Offset CA-CBh Default Value 0000h Access Size Bits ERRCMD-Error Command Register DeviceSingle-bit Dram ECC Error Flag Dserr Serr on Non-DRAM Lock Lckerr Serr on Invalid AGP Access Iaafserr Serr on AGP Access Outside of Graphics Aperture OogfserrSerr Multiple-Bit Dram ECC Error Dmerrserr Serr on Single-bit ECC Error Dserr SCICMD-SCI Command Register Device SMICMD-SMI Command Register DeviceAddress Offset CC-CDh Default Value 0000h Access Size Bits Address Offset CE-CDh Default Value 0000h Access Size Bits SKPD-Scratchpad Data Register Device Address Offset DE-DFh Default Value 0000h Access Size BitsAddress Offset E4h Default Value 0104A009h Access Size Bits Bridge Registers Device Address Symbol Name Default Access Drtc 1 VID1-Vendor Identification Register Device2 DID1-Device Identification Register Device Address Offset 04-05h Default 0000h Access PCICMD1-PCI-PCI Command Register DeviceParity Error Enable PERRE1-RO. Not Implemented Hardwired to Memory Access Enable MAE1-R/W Detected Parity Error DPE1-RO. Not Implemented Hardwired to Address Offset 06-07h Default Value 00A0h AccessSignaled System Error SSE1-R/WC PCISTS1-PCI-PCI Status Register Device 5 RID1-Revision Identification Register Device Address Offset 0Ah Default Value 04h Access Size BitsSUBC1-Sub-Class Code Register Device 7 BCC1-Base Class Code Register Device Offset 0Eh Default 01h Access Size Bits 8 MLT1-Master Latency Timer Register DeviceOffset 18h Default 00h Access Size Bits 9 HDR1-Header Type Register Device Offset 1Ah Default 00h Access Size Bits Offset 19h Default 00h Access Size BitsSBUSN1-Secondary Bus Number Register Device SUBUSN1-Subordinate Bus Number Register Device Address Offset 1Bh Default Value 00h Access Size Bits SMLT1-Secondary Master Latency Timer Register Device IOLIMIT1-I/O Limit Address Register Device IOBASE1-I/O Base Address Register Device Detected Parity Error DPE1-R/WC Address Offset 1E-1Fh Default Value 02A0h AccessSSTS1-Secondary PCI-PCI Status Register Device Received Master Abort Status RMAS1-R/WC Address Offset 22-23h Default Value 0000h Access Size Bits Address Offset 20-21h Default Value FFF0h Access Size BitsMBASE1-Memory Base Address Register Device MLIMIT1-Memory Limit Address Register Device Address Offset 26-27h Default Value 0000h Access Size Bits Address Offset 24-25h Default Value FFF0h Access Size BitsPMBASE1-Prefetchable Memory Base Address Register Device PMLIMIT1-Prefetchable Memory Limit Address Register Device BCTRL1-PCI-PCI Bridge Control Register Device Address Offset 3Eh Default 00h Access Serr on Receiving Target Abort Serta ERRCMD1-Error Command Register DeviceAddress Offset 40h Default Value 00h Access Size Bits DWTC-DRAM Write Thermal Management Control Register Device Address Offset 50-57h Default Value 00h Access Size BitsWrite Thermal Management Mode WTMMode DRTC-DRAM Read Thermal Management Control Register Device Read Thermal Management Mode RTMMode This page is intentionally left blank Addressable Memory Space Memory Address Ranges DOS Compatible Area Address Map Vgab VGA and MDA Memory Space ISA Hole Memory Space PAM Memory Spaces Ioapic Memory Space Tseg SMM Memory SpaceSystem Bus Interrupt Apic Memory Space High SMM Memory Space AGP Aperture Space Device 0 BAR AGP Memory Address RangesAGP Memory and Prefetchable Memory Hub Interface Subtractive Decode AGP Dram Graphics Aperture System Management Mode SMM Memory Range SMM Space Restrictions SMM Space DefinitionSMM Space Address Ranges Tseg Hub Interface Decode Rules I/O Address SpaceIntel MCH Decode Rules and Cross-Bridge Address Mapping AGP Interface Decode Rules Cycles Initiated Using AGP FRAME# Protocol DBI30# System BusDynamic Bus Inversion Upstream Interrupt Messages System Bus Interrupt Delivery Supported Dimm Configurations Memory Organization and ConfigurationSystem Memory Interface Single Data Rate SDR Sdram Interface Overview Byte Function Data Bytes on Dimm Used for Programming Dram Registers Address Translation and Decoding Memory Address Translation and Decoding AGP Target Operations AGP Interface OverviewDram Performance Description Response as PCIx Target BE30# MCH Host Bridge Command Encoding AGP Transaction Ordering AGP Signal Levels4 4x AGP Protocol Fast Writes Data Rate Control Bits PCI Command BE30# Intel MCH EncodingAGP FRAME# Transactions on AGP 116 Processor Power State Control Power and Thermal Management Sleep State Control Intel MCH System Reset and Power SequencingIntel MCH Clocking Power Characteristics Power CharacteristicsAbsolute Maximum Ratings Absolute Maximum Ratings Signal Signal Type Signals Signal GroupsSignal Groups BCLK, BCLK# DC Characteristics DC Characteristics Intel 82845 MCH for SDR Datasheet 123 124 Ballout and Package Information Intel 82845 MCH Ballout Diagram Top View-Left Side Intel 82845 MCH Ballout Diagram Top View-Right Side Signal Name Ball # AA2 HADSTB0# HADSTB1#AB5 AA5 130 SBA5 SBA4SBA6 SBA7 132 VSSA0 VSSA1 Package Mechanical Information Intel MCH FC-BGA Package Dimensions Top and Side View Intel MCH FC-BGA Package Dimensions Bottom View 136 XOR Tree Chain XOR Test Mode Initialization XOR Chains Chain 0 Ball Element # Signal Name Initial LogicXOR Chain AE6 HDSTBP1# SCK10 Chain 1 Ball Element # Signal Name Initial Logic SDQ65 Chain 2 Ball Element # Signal Name Initial Logic LevelSDQ22 SDQ64 Chain 3 Ball Element # Signal Name Initial Logic LevelSBCS1 Adstb Chain 4 Ball Element # Signal Name Initial Logic Level Gado Chain 5 Ball Element # Signal Name Initial Logic Level Intel 82845 MCH for SDR Datasheet 145 AH9 DBI2# Chain 6 Ball Element # Signal Name Initial Logic Level AE6 HDSTBN1# Chain 7 Ball Element # SDR Ball name Initial Logic LevelAD5 DBI0# AD4 HDSTBN0# 148