
Introduction
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1 Introduction
The Intel® 82845 Memory Controller Hub (MCH) is designed for use with the Intel® Pentium® 4 processor in the
This document describes the 82845 Memory Controller Hub (MCH) for use with SDR (Single Data Rate) memory devices. Section 1.3 provides an overview of the 845 chipset.
1.1Terminology and Notations
This section provides the definitions of some of the terms used in this document. Notations used for data types and numbers are also included. In addition, Section 3.1 contains register terminology definitions.
Table 1. General Terminology
Term | Description |
|
|
MCH | The Memory Controller Hub component that contains the processor interface, System |
| Memory DRAM controller, and AGP interface. It communicates with the I/O controller |
| hub (ICH2) and other IO controller hubs over proprietary interconnect called the hub |
| interface. |
|
|
ICH2 | The I/O Controller Hub component that contains the primary PCI interface, LPC |
| interface, USB, |
| MCH over a proprietary interconnect called the hub interface. |
|
|
Host | This term is used synonymously with processor. |
|
|
Core | The internal base logic in the MCH. |
|
|
System Bus | |
| pumped clock. It consists of source synchronous transfers for address and data, and |
| system bus interrupt delivery. |
|
|
Hub Interface | The proprietary hub interconnect that connects the MCH to the ICH2. In this document |
| hub interface cycles originating from or destined for the primary PCI interface on the |
| ICH2 are generally referred to as hub interface cycles. |
|
|
Accelerated | Refers to the AGP interface that is in the MCH. The MCH supports AGP 2.0 compliant |
Graphics Port | components only with 1.5 V signaling level. PIPE# and SBA addressing cycles and their |
(AGP) | associated data phases are generally referred to as AGP transactions. FRAME# cycles |
| over the AGP bus are generally referred to as AGP/PCI transactions. |
|
|
PCI_A | The physical PCI bus, driven directly by the ICH2 component. It supports 5 V, |
| 33 MHz PCI 2.2 compliant components. Communication between PCI_A and the MCH |
| occurs over the hub interface. |
| Note: Even though this PCI bus is referred to as PCI_A, it is not PCI Bus #0 from a |
| configuration standpoint. |
|
|
Full Reset | A full MCH reset is defined in this document when RSTIN# is asserted. |
|
|
Intel® 82845 MCH for SDR Datasheet | 11 |