
Register Description
R
3.5.18DRC—DRAM Controller Mode Register (Device 0)
Offset: |
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Default: | 00000000h | |
Access: | R/W, RO | |
Size: | 32 bits | |
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| Bit | Description |
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| 31:30 | Revision Number |
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| register definition. Currently, this field must be 00, since this revision (rev 00) is the only existing |
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| version of the specification. |
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| 29 | Initialization Complete |
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| between the memory controller and the BIOS. BIOS sets this bit to 1 after initialization of the |
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| DRAM memory array is complete. |
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| 28 | Dynamic Powerdown Mode |
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| pair of rows into powerdown mode when all banks are |
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| accessed, the relevant pair of rows is taken out of powerdown mode. |
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| The entry into powerdown mode is performed by |
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| activation of CKE. |
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| 0 = Disable. System memory powerdown disabled |
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| 1 = Enable. System memory powerdown enabled |
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| Note: Dynamic powerdown is a mobile only feature and not supported on desktop applications. |
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| 27:24 | Active SDRAM |
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| of SDRAM rows that may be active at once. |
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| 0000 = All rows allowed to be in the active state |
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| Others = Reserved. |
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| 23:22 | Reserved. |
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| 21:20 | DRAM Data Integrity Mode |
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| mode. |
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| 00 = |
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| 10 = Error checking with correction |
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| Other = Reserved |
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| 19:11 | Reserved. |
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| 10:8 | Refresh Mode Select |
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| so, at what rate refreshes will be executed. |
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| 000 = Reserved |
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| 001 = Refresh enabled. Refresh interval 15.6 us |
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| 010 = Refresh enabled. Refresh interval 7.8 us |
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| 011 = Refresh enabled. Refresh interval 64 us |
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| 111 = Refresh enabled. Refresh interval 64 clocks (fast refresh mode) |
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| Other = Reserved |
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| 7 | Reserved. |
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56 |
| Intel® 82845 MCH for SDR Datasheet |