System Bus Interrupt Delivery | Intel 845 specs

Functional Description

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5.1.2System Bus Interrupt Delivery

The Pentium 4 processor supports the system bus interrupt delivery; the APIC serial bus interrupt delivery mechanism is not supported. Interrupt-related messages are encoded on the system bus as “Interrupt Message Transactions”. In an 845 chipset platform, system bus interrupts can originate from the processor on the system bus, or from a downstream device on the hub interface or AGP. In the later case the MCH drives the “Interrupt Message Transaction” onto the system bus.

In an 845 chipset platform, the ICH2 contains IOxAPICs, and its interrupts are generated as upstream hub interface memory writes. Furthermore, PCI 2.2 defines MSIs (Message Signaled Interrupts) that are also in the form of memory writes. A PCI 2.2 device can generate an interrupt as an MSI cycle on it’s PCI bus, instead of asserting a hardware signal to the IOxAPIC. The MSI can be directed to the IOxAPIC, which in turn generates an interrupt as an upstream hub interface memory write. Alternatively, the MSI can be directed directly to the system bus. The target of a MSI is dependent on the address of the interrupt memory write. The MCH forwards inbound hub interface and AGP (PCI semantic only) memory writes to address 0FEEx_xxxxh, to the system bus as “Interrupt Message Transactions”.

5.1.3Upstream Interrupt Messages

The MCH accepts message-based interrupts from AGP (PCI semantics only) or its hub interface and forwards them to the system bus as Interrupt Message Transactions. The interrupt messages presented to the MCH are in the form of memory writes to address 0FEEx_xxxxh. At the hub interface or AGP interface, the memory write interrupt message is treated like any other memory write; it is either posted to the inbound data buffer (if space is available) or retried (if data buffer space is not immediately available). Once posted, the memory write from AGP or the hub interface to address 0FEEx_xxxxh is decoded as a cycle that needs to be propagated by the MCH to the system bus as an Interrupt Message Transaction.

108	Intel® 82845 MCH for SDR Datasheet

Image 108

Intel 845 manual System Bus Interrupt Delivery, Upstream Interrupt Messages

Contents

Intel 845 Chipset 82845 Memory Controller Hub MCH for SDR Document Number Intel 82845 MCH for SDR Datasheet Contents Register Device SMLT1-Secondary Master Latency Timer Register Device System Management Mode SMM Memory Range 103PMBASE1-Prefetchable Memory Base Address PMLIMIT1-Prefetchable Memory Limit Address 114 115117 118 Tables Revision History Revision Description Date Intel 82845 MCH Features System Block Diagram Terminology and Notations General TerminologyTerm Description Data Type Notation Number Format NotationData Type Size Number Format Notation Example Reference Documents Document Intel 845 Chipset System Architecture Intel 82845 MCH Overview System Bus Error Checking System Bus Interface System Memory Interface AGP InterfaceMemory Capacity Technology SDR PC133 Hub Interface Intel MCH ClockingIntel MCH Clock Ratio Table Interface Speed Processor Bclk Powerdown Flow System Interrupts Signal Description Intel MCH Simplified Block Diagram System Bus Signals Signal Name Type DescriptionDBIx# Data Bits Strobe Address Bits Strobe Data Bits RS20 Response Type SDR Sdram Interface Signals Hub Interface SignalsSdram Column Address Strobe SCAS# is used with SRAS# AGP Interface Signals AGP Addressing SignalsDuring SBA Operation Not Used During FRAME# Operation Not Used AGP Flow Control Signals AGP Status SignalsRBF# WBF# AGP Strobes Signals 5 AGP/PCI Signals Command/Byte Enable Parity Clocks, Reset, and Miscellaneous Signals BclkBCLK# Cmos RSTIN# Voltage Reference and Power Signals AGTL+ Bus Termination Voltage Inputs These pins provideSystem Memory Rcomp Reset States During Reset Signal NameState System Bus Interface Register Description Register Terminology PCI Bus Configuration Space Access Intel MCH Internal Device AssignmentsMCH Function Bus 0, Device # Standard PCI Bus Configuration Mechanism Routing Configuration Accesses CONFADDR-Configuration Address Register I/O Mapped Registers Configuration Enable Cfge Bit Descriptions CONFDATA-Configuration Data Register Address 0CFCh Default Value 00000000h Access Size BitsMemory-Mapped Register Space Memory-mapped Register Address Map Address Offset 2Ch Default Value 00h Access Size Bits DRAMWIDTH-DRAM Width RegisterRow Parameters SDR Clocks Affected DQCMDSTR-Strength Control Register SDQ and CMD Signal Groups CKESTR-Strength Control Register Scke Signal Group Memory Address Offset 31h Default Value 00h Access Size Bits CSBSTR-Strength Control Register SCS# Signal Group Memory Address Offset 32h Default Value 00h Access Size Bits CKSTR-Strength Control Register Clock Signal Group Memory Address Offset 33h Default Value 00h Access Size Bits RCVENSTR-Strength Control Register Rcvenout Signal Group Memory Address Offset 34h Default Value 00h Access Size Bits Intel MCH Configuration Space Device Address Register Register Name Default AccessHost-Hub Interface Bridge Device Registers Device Value EAP FdhcSmram Esmramc VID-Vendor Identification Register Device DID-Device Identification Register DeviceBit Description Bit Description PCICMD-PCI Command Register Device Address Offset 04-05h Default 0006h Access Size Bits Address Offset 06-07h Default Value 0090h Access PCISTS-PCI Status Register DeviceSize Bits Address Offset 0Ah Default Value 00h Access Size Bits Address Offset 0Bh Default Value 06h Access Size BitsRID-Revision Identification Register Device SUBC-Sub-Class Code Register Device MLT-Master Latency Timer Register Device Address Offset 0Dh Default Value 00h Access Size BitsAddress Offset 0Eh Default 00h Access Size Bits Bit Description Hardwired to 00h. Writes have no effect APBASE-Aperture Base Configuration Register Device Offset 10-13h Default 00000008h Access Size Bits SVID-Subsystem Vendor Identification Device SID-Subsystem Identification DeviceCAPPTR-Capabilities Pointer Device AGPM-AGP Miscellaneous Configuration Register Device Address Offset 51h Default Value 00h Access Size BitsOffset 60-67h DRB0-DRB7 Default 00h Access Size Bits 15 DRB07-DRAM Row Boundary Registers Device Offset 70-73h DRA0-DRA3 Default 00h Access Size Bits DRA-DRAM Row Attribute Registers Device Corresponding row Offset 78-7Bh Default 00000010h Access Size Bits DRT-DRAM Timing Register Device DRC-DRAM Controller Mode Register Device Offset 7C-7Fh Default 00000000h Access Size Bits = Normal operation DERRSYN-DRAM Error Syndrome Register Device EAP-Error Address Pointer Register DeviceAddress Offset 86h Default Value 00h Access Size Bits 21 PAM06-Programmable Attribute Map Registers Device Bits 7 Bits 6 Bits 5 Bits 4 Description PAM Register Attributes PAM6 PAM5 PAM4 PAM3 PAM2 PAM1 PAM0 DOS Application Area 00000h-9FFFh PAM Reg Attribute Bits Memory Segment Comments Offset Address Offset 97h Default Value 00h Access Size Bits FDHC-Fixed Dram Hole Control Register Device Global Smram Enable GSMRAME-R/W/L SMRAM-System Management RAM Control Register Device SMRAMCache SMCACHE-RO. Hardwired to SMRAML1EN SML1-RO. Hardwired toSMRAML2EN SML2-RO. Hardwired to ESMRAMC-Extended System Mgmt RAM Control Register Device ACAPID-AGP Capability Identifier Register Device AGPSTAT-AGP Status Register Device This register reports AGP device capability/status AGPCMD-AGP Command Register Device SideBand Address Enable SbaenAGP Enable Agpen Fast Write Enable Fwen AGPCTRL-AGP Control Register Device Data Rate 4x Override Address Offset B4h Default Value 00h Access Size Bits APSIZE-Aperture Size DeviceAperture Size ATTBASE-Aperture Translation Table Base Register Device AMTT-AGP Interface Multi-Transaction Timer Register Device Address Offset BCh Default Value 00h Access Size Bits LPTT-AGP Low Priority Transaction Timer Register Device Address Offset BDh Default Value 00h Access Size Bits Address Offset C4-C5h Default Value 0100h Access Size Bits TOM-Top of Low Memory Register Device MCHCFG-MCH Configuration Register Device Offset C6-C7h Default 0000h Access Size BitsApic Memory Range Disable APICDIS-R/W ERRSTS-Error Status Register Device Address Offset C8-C9h Default Value 0000h Access Size Bits ERRCMD-Error Command Register Device Address Offset CA-CBh Default Value 0000h Access Size BitsSingle-bit Dram ECC Error Flag Dserr Serr on Non-DRAM Lock Lckerr Serr on AGP Access Outside of Graphics Aperture Oogfserr Serr on Invalid AGP Access IaafserrSerr Multiple-Bit Dram ECC Error Dmerrserr Serr on Single-bit ECC Error Dserr SMICMD-SMI Command Register Device SCICMD-SCI Command Register DeviceAddress Offset CC-CDh Default Value 0000h Access Size Bits Address Offset CE-CDh Default Value 0000h Access Size Bits Address Offset DE-DFh Default Value 0000h Access Size Bits Address Offset E4h Default Value 0104A009h Access Size BitsSKPD-Scratchpad Data Register Device Address Symbol Name Default Access Bridge Registers Device 1 VID1-Vendor Identification Register Device 2 DID1-Device Identification Register DeviceDrtc PCICMD1-PCI-PCI Command Register Device Address Offset 04-05h Default 0000h AccessParity Error Enable PERRE1-RO. Not Implemented Hardwired to Memory Access Enable MAE1-R/W Address Offset 06-07h Default Value 00A0h Access Detected Parity Error DPE1-RO. Not Implemented Hardwired toSignaled System Error SSE1-R/WC PCISTS1-PCI-PCI Status Register Device Address Offset 0Ah Default Value 04h Access Size Bits 5 RID1-Revision Identification Register DeviceSUBC1-Sub-Class Code Register Device 7 BCC1-Base Class Code Register Device 8 MLT1-Master Latency Timer Register Device Offset 0Eh Default 01h Access Size BitsOffset 18h Default 00h Access Size Bits 9 HDR1-Header Type Register Device Offset 19h Default 00h Access Size Bits Offset 1Ah Default 00h Access Size BitsSBUSN1-Secondary Bus Number Register Device SUBUSN1-Subordinate Bus Number Register Device SMLT1-Secondary Master Latency Timer Register Device Address Offset 1Bh Default Value 00h Access Size Bits IOBASE1-I/O Base Address Register Device IOLIMIT1-I/O Limit Address Register Device Address Offset 1E-1Fh Default Value 02A0h Access Detected Parity Error DPE1-R/WCSSTS1-Secondary PCI-PCI Status Register Device Received Master Abort Status RMAS1-R/WC Address Offset 20-21h Default Value FFF0h Access Size Bits Address Offset 22-23h Default Value 0000h Access Size BitsMBASE1-Memory Base Address Register Device MLIMIT1-Memory Limit Address Register Device Address Offset 24-25h Default Value FFF0h Access Size Bits Address Offset 26-27h Default Value 0000h Access Size BitsPMBASE1-Prefetchable Memory Base Address Register Device PMLIMIT1-Prefetchable Memory Limit Address Register Device Address Offset 3Eh Default 00h Access BCTRL1-PCI-PCI Bridge Control Register Device ERRCMD1-Error Command Register Device Address Offset 40h Default Value 00h Access Size BitsSerr on Receiving Target Abort Serta Address Offset 50-57h Default Value 00h Access Size Bits Write Thermal Management Mode WTMModeDWTC-DRAM Write Thermal Management Control Register Device Read Thermal Management Mode RTMMode DRTC-DRAM Read Thermal Management Control Register Device This page is intentionally left blank Memory Address Ranges Addressable Memory Space DOS Compatible Area Address Map VGA and MDA Memory Space Vgab PAM Memory Spaces ISA Hole Memory Space Tseg SMM Memory Space Ioapic Memory SpaceSystem Bus Interrupt Apic Memory Space High SMM Memory Space AGP Memory Address Ranges AGP Aperture Space Device 0 BARAGP Memory and Prefetchable Memory Hub Interface Subtractive Decode System Management Mode SMM Memory Range AGP Dram Graphics Aperture SMM Space Definition SMM Space RestrictionsSMM Space Address Ranges Tseg I/O Address Space Intel MCH Decode Rules and Cross-Bridge Address MappingHub Interface Decode Rules Cycles Initiated Using AGP FRAME# Protocol AGP Interface Decode Rules System Bus Dynamic Bus InversionDBI30# System Bus Interrupt Delivery Upstream Interrupt Messages Memory Organization and Configuration Supported Dimm ConfigurationsSystem Memory Interface Single Data Rate SDR Sdram Interface Overview Data Bytes on Dimm Used for Programming Dram Registers Byte Function Memory Address Translation and Decoding Address Translation and Decoding AGP Interface Overview Dram Performance DescriptionAGP Target Operations BE30# MCH Host Bridge Command Encoding Response as PCIx Target AGP Signal Levels AGP Transaction Ordering4 4x AGP Protocol Fast Writes PCI Command BE30# Intel MCH Encoding AGP FRAME# Transactions on AGPData Rate Control Bits 116 Power and Thermal Management Processor Power State Control Intel MCH System Reset and Power Sequencing Intel MCH ClockingSleep State Control Power Characteristics Power CharacteristicsAbsolute Maximum Ratings Absolute Maximum Ratings Signal Groups Signal GroupsSignal Signal Type Signals BCLK, BCLK# DC Characteristics DC Characteristics Intel 82845 MCH for SDR Datasheet 123 124 Ballout and Package Information Intel 82845 MCH Ballout Diagram Top View-Left Side Intel 82845 MCH Ballout Diagram Top View-Right Side Signal Name Ball # HADSTB0# HADSTB1# AA2AB5 AA5 130 SBA4 SBA5SBA6 SBA7 132 VSSA1 VSSA0 Intel MCH FC-BGA Package Dimensions Top and Side View Package Mechanical Information Intel MCH FC-BGA Package Dimensions Bottom View 136 XOR Test Mode Initialization XOR Tree Chain Chain 0 Ball Element # Signal Name Initial Logic XOR ChainsXOR Chain AE6 HDSTBP1# SCK10 Chain 1 Ball Element # Signal Name Initial Logic Chain 2 Ball Element # Signal Name Initial Logic Level SDQ22SDQ65 Chain 3 Ball Element # Signal Name Initial Logic Level SBCS1SDQ64 Chain 4 Ball Element # Signal Name Initial Logic Level Adstb Chain 5 Ball Element # Signal Name Initial Logic Level Gado Intel 82845 MCH for SDR Datasheet 145 Chain 6 Ball Element # Signal Name Initial Logic Level AH9 DBI2# Chain 7 Ball Element # SDR Ball name Initial Logic Level AE6 HDSTBN1#AD5 DBI0# AD4 HDSTBN0# 148