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System Address Map
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4.1.8AGP Aperture Space (Device 0 BAR)
Processors and AGP devices communicate through a special buffer called the “graphics aperture” (APBASE to APBASE + APSIZE). This aperture acts as a window into main system memory and is defined by the APBASE and APSIZE configuration registers of the MCH. Note that the AGP aperture must be above the top of memory and must not intersect with any other address space.
4.1.9AGP Memory and Prefetchable Memory
• | M1 | MBASE1 to MLIMIT1 |
• | PM1 | PMBASE1 to PMLIMIT1 |
Note that these registers must be programmed with values that place the AGP memory space window between the value in the TOM register and 4 GB. In addition, neither region should overlap with any other fixed or relocatable area of memory.
4.1.10Hub Interface Subtractive Decode
All accesses that fall between the value programmed into the TOM register and 4 GB
(i.e., TOM to 4 GB) are subtractively decoded and forwarded to the hub interface if they do not decode to a space that corresponds to another device.
4.2AGP Memory Address Ranges
The MCH can be programmed to direct memory accesses to the AGP bus interface when addresses are within either of two ranges specified via registers in MCH device 1 configuration space. The first range is controlled via the Memory Base Address (MBASE1) register and Memory Limit Address (MLIMIT1) register. The second range is controlled via the Prefetchable Memory Base Address (PMBASE1) register and Prefetchable Memory Limit Address (PMLIMIT1) register
The MCH positively decodes memory accesses to AGP memory address space as defined by the following equations:
•Memory_Base_Address ≤ Address ≤ Memory_Limit_Address
•Prefetchable_Memory_Base_Address ≤ Address ≤ Prefetchable_Memory_Limit_Address
The
Note: The MCH device 1 memory range registers described above are used to allocate memory address space for any devices sitting on AGP bus that require such a window.
102 | Intel® 82845 MCH for SDR Datasheet |