Register Description
R
3.6.4PCISTS1—PCI-PCI Status Register (Device 1)
Address Offset: |
|
Default Value: | 00A0h |
Access: | RO, R/WC |
Size: | 16 bits |
PCISTS1 is a
Bit | Descriptions |
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15 | Detected Parity Error |
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14 | Signaled System Error |
| 0 =Software clears this bit by writing a 1 to it. |
| 1 =MCH device 1 generated an SERR message over the hub interface for any enabled Device |
| 1 error condition. Device 1 error conditions are enabled in the ERRCMD, PCICMD1 and |
| BCTRL1 registers. Device 1 error flags are read/reset from the ERRSTS and SSTS1 |
| register. |
|
|
13 | Received Master Abort Status |
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12 | Received Target Abort Status |
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11 | Signaled Target Abort Status |
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10:9 | DEVSEL# Timing |
| possible decode. |
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8 | Data Parity Detected (DPD1). Not Implemented; Hardwired to 0. |
|
|
7 | Fast |
| back transactions. |
|
|
6 | Reserved. |
|
|
5 | 66 MHz Capability |
| capable. |
|
|
4:0 | Reserved. |
|
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Intel® 82845 MCH for SDR Datasheet | 83 |