AGPCMD-AGP Command Register Device, AGP Enable Agpen | Intel 845

Register Description

R

3.5.27AGPCMD—AGP Command Register (Device 0)

Address Offset:	A8–ABh
Default Value:	0000_0000h
Access:	R/W
Size:	32 bits

This register provides control of the AGP operational parameters.

Bit		Description

31:10	Reserved.

9	SideBand Address Enable (SBAEN).
	0	= Disable.
	1	= Enable.

8	AGP Enable (AGPEN).
	0	= The MCH ignores all AGP operations, including the sync cycle. Any AGP operation received
		while this bit is 1 will be serviced, even if this bit is set to 0. If this bit transitions from a 1 to a 0
		on a clock edge in the middle of an SBA command being delivered in 1X mode, the command
		will be issued.
	1	= The MCH will respond to AGP operations delivered via PIPE# or to operations delivered via
		SBA if the AGP Side Band Enable bit is also set to 1.

7:5	Reserved.

4	Fast Write Enable (FWEN).
	0	= When this bit is set to 0, or when the data rate bits are set to 1x mode, the memory write
		transactions from the MCH to the AGP master use standard PCI protocol.
	1	= MCH uses the Fast Write protocol for memory write transactions from the MCH to the AGP
		master. Fast Writes occur at the data transfer rate selected by the DRATE bits (2:0) in this
		register.

3	Reserved.

2:0	Data Rate (DRATE). The settings of these bits determine the AGP data transfer rate. One (and
	only one) bit in this field must be set to indicate the desired data transfer rate.
	001 = 1x transfer mode
	010 = 2x transfer mode
	100 = 4x transfer mode
	Configuration software updates this field by setting only one bit that corresponds to the capability
	of AGP master (after that capability has been verified by accessing the same functional register
	in the AGP masters’ configuration space.)
	Note: This field applies to AD and SBA buses. It also applies to Fast Writes if they are enabled.

Intel® 82845 MCH for SDR Datasheet

67

Image 67

Intel 845 AGPCMD-AGP Command Register Device, SideBand Address Enable Sbaen, AGP Enable Agpen, Fast Write Enable Fwen

Contents

Document Number Intel 845 Chipset 82845 Memory Controller Hub MCH for SDR Intel 82845 MCH for SDR Datasheet Contents Register Device PMLIMIT1-Prefetchable Memory Limit Address SMLT1-Secondary Master Latency Timer Register DeviceSystem Management Mode SMM Memory Range 103 PMBASE1-Prefetchable Memory Base Address 118 114115 117 Tables Revision Description Date Revision History Intel 82845 MCH Features System Block Diagram General Terminology Terminology and NotationsTerm Description Number Format Notation Example Data Type NotationNumber Format Notation Data Type Size Document Reference Documents Intel 82845 MCH Overview Intel 845 Chipset System Architecture System Bus Interface System Bus Error Checking Technology SDR PC133 System Memory InterfaceAGP Interface Memory Capacity Interface Speed Processor Bclk Hub InterfaceIntel MCH Clocking Intel MCH Clock Ratio Table System Interrupts Powerdown Flow Signal Description Intel MCH Simplified Block Diagram Strobe Address Bits System Bus SignalsSignal Name Type Description DBIx# Data Bits RS20 Response Type Strobe Data Bits Hub Interface Signals SDR Sdram Interface SignalsSdram Column Address Strobe SCAS# is used with SRAS# During FRAME# Operation Not Used AGP Interface SignalsAGP Addressing Signals During SBA Operation Not Used WBF# AGP Flow Control SignalsAGP Status Signals RBF# 5 AGP/PCI Signals AGP Strobes Signals Parity Command/Byte Enable RSTIN# Clocks, Reset, and Miscellaneous SignalsBclk BCLK# Cmos AGTL+ Bus Termination Voltage Inputs These pins provide Voltage Reference and Power SignalsSystem Memory Rcomp System Bus Interface Reset States During ResetSignal Name State Register Terminology Register Description Intel MCH Internal Device Assignments PCI Bus Configuration Space AccessMCH Function Bus 0, Device # Routing Configuration Accesses Standard PCI Bus Configuration Mechanism I/O Mapped Registers CONFADDR-Configuration Address Register Bit Descriptions Configuration Enable Cfge Memory-mapped Register Address Map CONFDATA-Configuration Data RegisterAddress 0CFCh Default Value 00000000h Access Size Bits Memory-Mapped Register Space DRAMWIDTH-DRAM Width Register Address Offset 2Ch Default Value 00h Access Size BitsRow Parameters SDR Clocks Affected DQCMDSTR-Strength Control Register SDQ and CMD Signal Groups Memory Address Offset 31h Default Value 00h Access Size Bits CKESTR-Strength Control Register Scke Signal Group Memory Address Offset 32h Default Value 00h Access Size Bits CSBSTR-Strength Control Register SCS# Signal Group Memory Address Offset 33h Default Value 00h Access Size Bits CKSTR-Strength Control Register Clock Signal Group Memory Address Offset 34h Default Value 00h Access Size Bits RCVENSTR-Strength Control Register Rcvenout Signal Group Value Intel MCH Configuration Space DeviceAddress Register Register Name Default Access Host-Hub Interface Bridge Device Registers Device Esmramc EAPFdhc Smram Bit Description VID-Vendor Identification Register DeviceDID-Device Identification Register Device Bit Description Address Offset 04-05h Default 0006h Access Size Bits PCICMD-PCI Command Register Device PCISTS-PCI Status Register Device Address Offset 06-07h Default Value 0090h AccessSize Bits SUBC-Sub-Class Code Register Device Address Offset 0Ah Default Value 00h Access Size BitsAddress Offset 0Bh Default Value 06h Access Size Bits RID-Revision Identification Register Device Bit Description Hardwired to 00h. Writes have no effect MLT-Master Latency Timer Register DeviceAddress Offset 0Dh Default Value 00h Access Size Bits Address Offset 0Eh Default 00h Access Size Bits Offset 10-13h Default 00000008h Access Size Bits APBASE-Aperture Base Configuration Register Device SID-Subsystem Identification Device SVID-Subsystem Vendor Identification DeviceCAPPTR-Capabilities Pointer Device 15 DRB07-DRAM Row Boundary Registers Device AGPM-AGP Miscellaneous Configuration Register DeviceAddress Offset 51h Default Value 00h Access Size Bits Offset 60-67h DRB0-DRB7 Default 00h Access Size Bits DRA-DRAM Row Attribute Registers Device Offset 70-73h DRA0-DRA3 Default 00h Access Size Bits Corresponding row DRT-DRAM Timing Register Device Offset 78-7Bh Default 00000010h Access Size Bits Offset 7C-7Fh Default 00000000h Access Size Bits DRC-DRAM Controller Mode Register Device = Normal operation EAP-Error Address Pointer Register Device DERRSYN-DRAM Error Syndrome Register DeviceAddress Offset 86h Default Value 00h Access Size Bits Bits 7 Bits 6 Bits 5 Bits 4 Description 21 PAM06-Programmable Attribute Map Registers Device PAM6 PAM5 PAM4 PAM3 PAM2 PAM1 PAM0 PAM Register Attributes PAM Reg Attribute Bits Memory Segment Comments Offset DOS Application Area 00000h-9FFFh FDHC-Fixed Dram Hole Control Register Device Address Offset 97h Default Value 00h Access Size Bits SMRAM-System Management RAM Control Register Device Global Smram Enable GSMRAME-R/W/L ESMRAMC-Extended System Mgmt RAM Control Register Device SMRAMCache SMCACHE-RO. Hardwired toSMRAML1EN SML1-RO. Hardwired to SMRAML2EN SML2-RO. Hardwired to ACAPID-AGP Capability Identifier Register Device This register reports AGP device capability/status AGPSTAT-AGP Status Register Device Fast Write Enable Fwen AGPCMD-AGP Command Register DeviceSideBand Address Enable Sbaen AGP Enable Agpen Data Rate 4x Override AGPCTRL-AGP Control Register Device APSIZE-Aperture Size Device Address Offset B4h Default Value 00h Access Size BitsAperture Size ATTBASE-Aperture Translation Table Base Register Device Address Offset BCh Default Value 00h Access Size Bits AMTT-AGP Interface Multi-Transaction Timer Register Device Address Offset BDh Default Value 00h Access Size Bits LPTT-AGP Low Priority Transaction Timer Register Device TOM-Top of Low Memory Register Device Address Offset C4-C5h Default Value 0100h Access Size Bits Offset C6-C7h Default 0000h Access Size Bits MCHCFG-MCH Configuration Register DeviceApic Memory Range Disable APICDIS-R/W Address Offset C8-C9h Default Value 0000h Access Size Bits ERRSTS-Error Status Register Device Serr on Non-DRAM Lock Lckerr ERRCMD-Error Command Register DeviceAddress Offset CA-CBh Default Value 0000h Access Size Bits Single-bit Dram ECC Error Flag Dserr Serr on Single-bit ECC Error Dserr Serr on AGP Access Outside of Graphics Aperture OogfserrSerr on Invalid AGP Access Iaafserr Serr Multiple-Bit Dram ECC Error Dmerrserr Address Offset CE-CDh Default Value 0000h Access Size Bits SMICMD-SMI Command Register DeviceSCICMD-SCI Command Register Device Address Offset CC-CDh Default Value 0000h Access Size Bits Address Offset E4h Default Value 0104A009h Access Size Bits Address Offset DE-DFh Default Value 0000h Access Size BitsSKPD-Scratchpad Data Register Device Bridge Registers Device Address Symbol Name Default Access 2 DID1-Device Identification Register Device 1 VID1-Vendor Identification Register DeviceDrtc Memory Access Enable MAE1-R/W PCICMD1-PCI-PCI Command Register DeviceAddress Offset 04-05h Default 0000h Access Parity Error Enable PERRE1-RO. Not Implemented Hardwired to PCISTS1-PCI-PCI Status Register Device Address Offset 06-07h Default Value 00A0h AccessDetected Parity Error DPE1-RO. Not Implemented Hardwired to Signaled System Error SSE1-R/WC 7 BCC1-Base Class Code Register Device Address Offset 0Ah Default Value 04h Access Size Bits5 RID1-Revision Identification Register Device SUBC1-Sub-Class Code Register Device 9 HDR1-Header Type Register Device 8 MLT1-Master Latency Timer Register DeviceOffset 0Eh Default 01h Access Size Bits Offset 18h Default 00h Access Size Bits SUBUSN1-Subordinate Bus Number Register Device Offset 19h Default 00h Access Size BitsOffset 1Ah Default 00h Access Size Bits SBUSN1-Secondary Bus Number Register Device Address Offset 1Bh Default Value 00h Access Size Bits SMLT1-Secondary Master Latency Timer Register Device IOLIMIT1-I/O Limit Address Register Device IOBASE1-I/O Base Address Register Device Received Master Abort Status RMAS1-R/WC Address Offset 1E-1Fh Default Value 02A0h AccessDetected Parity Error DPE1-R/WC SSTS1-Secondary PCI-PCI Status Register Device MLIMIT1-Memory Limit Address Register Device Address Offset 20-21h Default Value FFF0h Access Size BitsAddress Offset 22-23h Default Value 0000h Access Size Bits MBASE1-Memory Base Address Register Device PMLIMIT1-Prefetchable Memory Limit Address Register Device Address Offset 24-25h Default Value FFF0h Access Size BitsAddress Offset 26-27h Default Value 0000h Access Size Bits PMBASE1-Prefetchable Memory Base Address Register Device BCTRL1-PCI-PCI Bridge Control Register Device Address Offset 3Eh Default 00h Access Address Offset 40h Default Value 00h Access Size Bits ERRCMD1-Error Command Register DeviceSerr on Receiving Target Abort Serta Write Thermal Management Mode WTMMode Address Offset 50-57h Default Value 00h Access Size BitsDWTC-DRAM Write Thermal Management Control Register Device DRTC-DRAM Read Thermal Management Control Register Device Read Thermal Management Mode RTMMode This page is intentionally left blank Addressable Memory Space Memory Address Ranges DOS Compatible Area Address Map Vgab VGA and MDA Memory Space ISA Hole Memory Space PAM Memory Spaces High SMM Memory Space Tseg SMM Memory SpaceIoapic Memory Space System Bus Interrupt Apic Memory Space Hub Interface Subtractive Decode AGP Memory Address RangesAGP Aperture Space Device 0 BAR AGP Memory and Prefetchable Memory AGP Dram Graphics Aperture System Management Mode SMM Memory Range Tseg SMM Space DefinitionSMM Space Restrictions SMM Space Address Ranges Intel MCH Decode Rules and Cross-Bridge Address Mapping I/O Address SpaceHub Interface Decode Rules AGP Interface Decode Rules Cycles Initiated Using AGP FRAME# Protocol Dynamic Bus Inversion System BusDBI30# Upstream Interrupt Messages System Bus Interrupt Delivery Single Data Rate SDR Sdram Interface Overview Memory Organization and ConfigurationSupported Dimm Configurations System Memory Interface Byte Function Data Bytes on Dimm Used for Programming Dram Registers Address Translation and Decoding Memory Address Translation and Decoding Dram Performance Description AGP Interface OverviewAGP Target Operations Response as PCIx Target BE30# MCH Host Bridge Command Encoding Fast Writes AGP Signal LevelsAGP Transaction Ordering 4 4x AGP Protocol AGP FRAME# Transactions on AGP PCI Command BE30# Intel MCH EncodingData Rate Control Bits 116 Processor Power State Control Power and Thermal Management Intel MCH Clocking Intel MCH System Reset and Power SequencingSleep State Control Absolute Maximum Ratings Power CharacteristicsPower Characteristics Absolute Maximum Ratings Signal Groups Signal GroupsSignal Signal Type Signals BCLK, BCLK# DC Characteristics DC Characteristics Intel 82845 MCH for SDR Datasheet 123 124 Ballout and Package Information Intel 82845 MCH Ballout Diagram Top View-Left Side Intel 82845 MCH Ballout Diagram Top View-Right Side Signal Name Ball # AA5 HADSTB0# HADSTB1#AA2 AB5 130 SBA7 SBA4SBA5 SBA6 132 VSSA0 VSSA1 Package Mechanical Information Intel MCH FC-BGA Package Dimensions Top and Side View Intel MCH FC-BGA Package Dimensions Bottom View 136 XOR Tree Chain XOR Test Mode Initialization AE6 HDSTBP1# Chain 0 Ball Element # Signal Name Initial LogicXOR Chains XOR Chain SCK10 Chain 1 Ball Element # Signal Name Initial Logic SDQ22 Chain 2 Ball Element # Signal Name Initial Logic LevelSDQ65 SBCS1 Chain 3 Ball Element # Signal Name Initial Logic LevelSDQ64 Adstb Chain 4 Ball Element # Signal Name Initial Logic Level Gado Chain 5 Ball Element # Signal Name Initial Logic Level Intel 82845 MCH for SDR Datasheet 145 AH9 DBI2# Chain 6 Ball Element # Signal Name Initial Logic Level AD4 HDSTBN0# Chain 7 Ball Element # SDR Ball name Initial Logic LevelAE6 HDSTBN1# AD5 DBI0# 148