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Register Description
R
3.5.29APSIZE—Aperture Size (Device 0)
Address Offset: | B4h |
Default Value: | 00h |
Access: | R/W |
Size: | 8 bits |
This register determines the effective size of the Graphics Aperture used for a particular MCH configuration. This register can be updated by the MCH specific BIOS configuration sequence before the PCI standard bus enumeration sequence takes place. If the register is not updated, the default value will select an aperture of maximum size (i.e., 256 MB). The size of the table that will correspond to a 256 MB aperture is not practical for most applications; therefore, these bits must be programmed to a smaller practical value that will force adequate address range to be requested via APBASE register from the PCI configuration software.
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7:6 | Reserved. |
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5:0 | Graphics Aperture Size (APSIZE). Each bit in APSIZE[5:0] operates on similarly ordered bits in | ||||||
| APBASE[27:22] of the Aperture Base configuration register. When a particular bit of this field is 0, | ||||||
| it forces the similarly ordered bit in APBASE[27:22] to behave as “hardwired” to 0. When a | ||||||
| particular bit of this field is set to 1, it allows corresponding bit of the APBASE[27:22] to be | ||||||
| read/write accessible. Only the following combinations are allowed: | ||||||
| 5 | 4 | 3 | 2 | 1 | 0 | Aperture Size |
| 1 | 1 | 1 | 1 | 1 | 1 | 4 MB |
| 1 | 1 | 1 | 1 | 1 | 0 | 8 MB |
| 1 | 1 | 1 | 1 | 0 | 0 | 16 MB |
| 1 | 1 | 1 | 0 | 0 | 0 | 32 MB |
| 1 | 1 | 0 | 0 | 0 | 0 | 64 MB |
| 1 | 0 | 0 | 0 | 0 | 0 | 128 MB |
| 0 | 0 | 0 | 0 | 0 | 0 | 256 MB |
| Default for APSIZE[5:0]=000000b forces default APBASE[27:22] =000000b (i.e., all bits respond | ||||||
| as “hardwired” to 0). This provides maximum aperture size of 256 MB. As another example, | ||||||
| programming APSIZE[5:0]=111000b hardwires APBASE[24:22]=000b and while enabling | ||||||
| APBASE[27:25] as read/write. | ||||||
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Intel® 82845 MCH for SDR Datasheet | 69 |