
Register Description
R
3.5.8MLT—Master Latency Timer Register (Device 0)
Address Offset: | 0Dh |
Default Value: | 00h |
Access: | RO |
Size: | 8 bits |
The hub interface does not comprehend the concept of Master Latency Timer. Therefore, this register is not implemented.
Bit | Description |
|
|
7:0 | Hardwired to 00h. Writes have no effect. |
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3.5.9HDR—Header Type Register (Device 0)
Address Offset: | 0Eh |
Default: | 00h |
Access: | RO |
Size: | 8 bits |
This register identifies the header layout of the configuration space.
Bit | Description |
|
|
7:0 | Hardwired to 00h. Writes have no effect. |
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Intel® 82845 MCH for SDR Datasheet | 49 |