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Register Description
R
3.6.21BCTRL1—PCI-PCI Bridge Control Register (Device 1)
Address Offset: | 3Eh |
Default: | 00h |
Access: | RO, R/W |
Size | 8 bits |
This register provides extensions to the PCICMD1 register that are specific to
| Bit | Descriptions |
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| 7 | Fast Back to Back Enable |
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| allowed on AGP, this bit is meaningless. The MCH will not generate FB2B cycles in 1x mode, but |
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| will generate FB2B cycles in 2x and 4x Fast Write modes. |
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| 6 | Secondary Bus Reset |
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| reset via this bit on the AGP. |
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| Note: The only way to perform a hard reset of the AGP is via the system reset either initiated by |
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| software or hardware via the ICH2. |
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| 5 | Master Abort Mode |
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| on AGP and a Master Abort occurs, the MCH will discard data on writes and return all 1s during |
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| reads. |
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| 4 | Reserved. |
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| 3 | VGA Enable |
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| targeting VGA compatible I/O and memory address ranges. |
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| 0 =VGA compatible memory and I/O range accesses are not forwarded to AGP (Default). Rather, |
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| they are mapped to primary PCI unless they are mapped to AGP via I/O and memory range |
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| registers defined above (IOBASE1, IOLIMIT1, MBASE1, MLIMIT1, PMBASE1, PMLIMIT1) |
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| 1 =MCH forwards the following host accesses to the AGP: |
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| • Memory accesses in the range 0A0000h to 0BFFFFh |
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| • I/O addresses where A[9:0] are in the ranges 3B0h to 3BBh and 3C0h to 3DFh |
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| (inclusive of ISA address aliases - A[15:10] are not decoded) |
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| When this bit is set, forwarding of these accesses issued by the host is independent of the I/O |
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| address and memory address ranges defined by the previously defined base and limit |
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| registers. Forwarding of these accesses is also independent of the settings of bit 2 (ISA |
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| Enable) of this register if this bit is 1. |
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| Refer to Chapter 4 for further information. |
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| 2 | ISA Enable |
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| host that targets ISA I/O addresses. This applies only to I/O addresses that are enabled by the |
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| IOBASE and IOLIMIT registers. |
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| 0 =Disable. All addresses defined by the IOBASE and IOLIMIT Registers for host I/O |
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| transactions are mapped to AGP (Default). |
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| 1 =Enable. MCH does not forward to AGP any I/O transactions addressing the last 768 bytes in |
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| each 1 KB block, even if the addresses are within the range defined by the IOBASE and |
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| IOLIMIT registers. Instead of going to AGP, these cycles are forwarded to PCI0 where they |
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| can be subtractively or positively claimed by the ISA bridge. |
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| 1 | Reserved. |
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92 |
| Intel® 82845 MCH for SDR Datasheet |