Introduction

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1.4.1System Bus Interface

The MCH is optimized for the Pentium 4 processor. The primary enhancements over the Compatible Mode P6 bus protocol are:

Source synchronous double-pumped address

Source synchronous quad-pumped data

System bus interrupt and side-band signal delivery

The MCH supports a 64-byte cache line size. Only one processor is supported at a system bus frequency of 400 MHz. The MCH supports a 3:4 host-to-memory frequency ratio (using the

100 MHz clock). The MCH integrates AGTL+ termination resistors on all of the AGTL+ signals. The MCH supports 32-bit system bus addresses, allowing the processor to access the entire 4 GB of the MCH memory address space.

The MCH has a 12-deep In-Order Queue to support up to twelve outstanding pipelined address requests on the system bus. The MCH supports two outstanding defer cycles at a time; however, only one to any particular I/O interface. Processor-initiated I/O cycles are positively decoded to AGP/PCI or MCH configuration space and subtractively decoded to the hub interface. Processor- initiated memory cycles are positively decoded to AGP/PCI or system memory, and are again subtractively decoded to the hub interface, if under 4 GB. AGP semantic memory accesses initiated from AGP/PCI to system memory are not snooped on the system bus. Memory accesses initiated from AGP/PCI using PCI semantics and from the hub interface to system memory will be snooped on the system bus. Memory accesses whose addresses lie within the AGP aperture are translated using the AGP address translation table, regardless of the originating interface.

1.4.2System Bus Error Checking

The MCH does not generate parity, nor check parity for data, address/request, and response signals on the processor bus.

Intel® 82845 MCH for SDR Datasheet

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Intel 845 manual System Bus Interface, System Bus Error Checking