
Introduction
R
1.4.1System Bus Interface
The MCH is optimized for the Pentium 4 processor. The primary enhancements over the Compatible Mode P6 bus protocol are:
•Source synchronous
•Source synchronous
•System bus interrupt and
The MCH supports a
100 MHz clock). The MCH integrates AGTL+ termination resistors on all of the AGTL+ signals. The MCH supports
The MCH has a
1.4.2System Bus Error Checking
The MCH does not generate parity, nor check parity for data, address/request, and response signals on the processor bus.
Intel® 82845 MCH for SDR Datasheet | 15 |