Signal Description
R
Intel® 82845 MCH for SDR Datasheet 29
Signal Name Type Description
HVREF Ref Host Reference Voltage: Reference voltage input for the data, address,
and common clock signals of the host AGTL+ interface.
SDREF Ref SDRAM Reference Voltage: Reference voltage input for DQ, DQS,
RDCLKIN (SDR).
HI_REF Ref Hub Interface Reference: Reference voltage input for the hub interface.
AGPREF Ref AGP Reference: Reference voltage input for the AGP interface.
HLRCOMP I/O
CMOS Compensation for Hub Interface: This signal is us ed to calibrate the
hub interface I/O buffers. It is connected to a 40.2 Ω pull-up resistor with
1% tolerance and is pulled up to VCC1_8.
GRCOMP I/O
CMOS Compensation for AGP: This signal is used to calibrat e buf fers. It is
connected to a 40.2 Ω pull-down resistor with a 1% tolerance.
HRCOMP[1:0] I/O
CMOS Compensation for Host: These signals are used t o calibrate the host
AGTL+ I/O buffers. Each signal is connected to a 24.9 Ω pull-down
resistor with a 1% tolerance.
HSWNG[1:0] I
CMOS Host Reference Voltage: Reference voltage input f o r t he c ompensation
logic.
SMRCOMP I/O
CMOS System Memory RCOMP:
VCC1_5 1.5 V Power Input: These pins are connected to a 1.5 V power source.
VCC1_8 1.8 V Power Input Pins: These pins are connected to a 1.8 V power
source.
VCCSM SDRAM Power Input Pins: These pins are connected to a 3.3 V power
source for SDR.
VCCA[1:0] PLL Power Input Pins: These pins provide power for the PLL.
VTT AGTL+ Bus Termination Voltage Inputs: These pins provide the
AGTL+ bus termination.
VSS Ground: The VSS pins are the ground pins for the MCH.
VSSA[1:0] PLL Ground: The VSSA[1:0] pins are the ground pins for the PLL on
the MCH.