
Signal Description
R
2.6Voltage Reference and Power Signals
Signal Name | Type | Description |
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HVREF | Ref | Host Reference Voltage: Reference voltage input for the data, address, |
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| and common clock signals of the host AGTL+ interface. |
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SDREF | Ref | SDRAM Reference Voltage: Reference voltage input for DQ, DQS, |
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| RDCLKIN (SDR). |
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HI_REF | Ref | Hub Interface Reference: Reference voltage input for the hub interface. |
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AGPREF | Ref | AGP Reference: Reference voltage input for the AGP interface. |
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HLRCOMP | I/O | Compensation for Hub Interface: This signal is used to calibrate the |
| CMOS | hub interface I/O buffers. It is connected to a 40.2 Ω |
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| 1% tolerance and is pulled up to VCC1_8. |
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GRCOMP | I/O | Compensation for AGP: This signal is used to calibrate buffers. It is |
| CMOS | connected to a 40.2 Ω |
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HRCOMP[1:0] | I/O | Compensation for Host: These signals are used to calibrate the host |
| CMOS | AGTL+ I/O buffers. Each signal is connected to a 24.9 Ω |
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| resistor with a 1% tolerance. |
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HSWNG[1:0] | I | Host Reference Voltage: Reference voltage input for the compensation |
| CMOS | logic. |
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SMRCOMP | I/O | System Memory RCOMP: |
| CMOS |
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VCC1_5 |
| 1.5 V Power Input: These pins are connected to a 1.5 V power source. |
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VCC1_8 |
| 1.8 V Power Input Pins: These pins are connected to a 1.8 V power |
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| source. |
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VCCSM |
| SDRAM Power Input Pins: These pins are connected to a 3.3 V power |
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| source for SDR. |
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VCCA[1:0] |
| PLL Power Input Pins: These pins provide power for the PLL. |
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VTT |
| AGTL+ Bus Termination Voltage Inputs: These pins provide the |
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| AGTL+ bus termination. |
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VSS |
| Ground: The VSS pins are the ground pins for the MCH. |
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VSSA[1:0] |
| PLL Ground: The VSSA[1:0] pins are the ground pins for the PLL on |
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| the MCH. |
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Intel® 82845 MCH for SDR Datasheet | 29 |