Functional Description
R
116 Intel® 82845 MCH for SDR Datasheet
C/BE[3:0]# Intel® MCH PCI Command
Encoding Cycle Destination Response as a FRAME#
Target
Dual Address Cycle 1101 N/A No response
Memory Read Line 1110 System Mem ory Read
1110 Hub interface No res pons e
Memory Write and
Invalidate 1111 System memory Posts data
1111 Hub interface Posts Dat a
NOTES:
1. N/A ref ers to a function that is not applicable
As a target of an AGP FRAME# cycle, the MCH only supports the following transactions:
• Memory Read, Memory Read Line, and Memory Read Multiple. These commands are
supported identically by the MCH. The MCH does not support reads of the hub interface bus
from AGP.
• Memo ry Write and Memory Write and Invalidate. These commands are aliased and processed
identically.
• Other Commands. Other commands (e.g., I/O R/W and Configuration R/W) are not supported
by the MCH as a target and result in master abort.
• Exclusive Access. The MCH does not support PCI locked cycles as a target.
• Fast Back-to-Back Transactions. The MCH, as a target, supports fast back-to-back cycles
from an AGP FRAME# initiator.
As an initiator of AGP FRAME# cycle, the MCH only supports the following transactions:
• Memory Read and Memory Read Line. MCH supports reads from host to AGP. MCH does
not support reads from the hub interface to AGP.
• Memo ry Rea d Multiple. This command is not supported by the MCH as an AGP FRAME#
initiator.
• Memo ry Write. The MCH initiates AGP FRAME# cycles on behalf of the host or the hub
interface. As an initiator, the MCH does not issue Memory Write and Invalidate cycles. The
MCH does not support write merging or write collapsing. The MCH allows non-snoopable
write transactions from the hub interface to the AGP bus.
• I/O Read and Write. I/O read and write cycles from the host are sent to the AGP bus. The I/O
base and limit address range for the AGP bus are programmed in the configuration registers.
All other accesses that do not correspond to this programmed address range are forwarded to
the hub interface.
• Exclusive Access. The MCH does not issue a locked cycle on the AGP bus on behalf of either
the host or the hub interface. The hub interface and host locked transactions to AGP are
initiated as unlocked transactions by the MCH on the AGP bus.
• Configuration Read and Write. Host configuration cycles to AGP are forwarded as Type 1
configuration cycles.
• Fast Back-to-Back Transactions. The MCH, as an initiator, does not perform fast back-to-
back cycles.