
Functional Description
R
MCH Retry/Disconnect Conditions
The MCH generates retry/disconnect according to the AGP Interface Specification, Revision 2.0 rules when being accessed as a target from the AGP FRAME# device.
Delayed Transaction
When an AGP
The MCH latches the address and command when establishing a delayed transaction. The MCH generates a delayed transaction on the AGP only for AGP FRAME# to system memory read accesses. The MCH does not allow more than one delayed transaction access from AGP at any time.
5.4Power and Thermal Management
An 845 chipset platform is compliant with the following specifications:
•APM, Revision 1.2
•ACPI, Revision 1.0b
•PCI Power Management, Revision 1.0
•PC ’99, Revision 1.0
•PC ’99A
•PC ’01, Revision 1.0
5.4.1Processor Power State Control
•C0 (Full On): This is the only state that runs software. All clocks are running, STPCLK# is deasserted, and the processor core is active. The processor can service snoops and maintain cache coherency in this state.
•
Intel® 82845 MCH for SDR Datasheet | 117 |