System Interrupts, Powerdown Flow | Intel 845 specs

Introduction

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1.4.7System Interrupts

The MCH supports both Intel 8259 and Pentium 4 processor interrupt delivery mechanisms. The serial APIC interrupt mechanism is not supported.

Intel 8259 support consists of flushing inbound hub interface write buffers when an Interrupt Acknowledge cycle is forwarded from the system bus to the hub interface.

The MCH supports the Pentium 4 processor interrupt delivery mechanism. IOxAPIC and PCI MSI interrupts are generated as memory writes. The MCH decodes upstream memory writes to the range 0FEE0_0000h–0FEEF_FFFFh from AGP and the hub interface as message-based interrupts. The MCH forwards the memory writes, along with the associated write data, to the system bus as an interrupt message transaction. Note that since this address does not decode as part of system memory, the write cycle and the write data are not forwarded to system memory via the write buffer. The MCH provides the response and TRDY# for all interrupt message cycles, including the ones originating from the MCH. The MCH supports interrupt re-direction for inter-processor interrupts (IPIs) as well as upstream interrupt memory writes.

For message-based interrupts, system write-buffer coherency is maintained by relying on strict ordering of memory writes. The MCH ensures that all memory writes received from a given interface prior to an interrupt message memory write are delivered to the system bus for snooping in the same order that they occur on the given interface.

1.4.8Powerdown Flow

Since the MCH is powered down during STR, the MCH cannot maintain any state information when exiting STR. Thus, the entire initialization process when exiting STR must be performed by the BIOS via accesses to the DRC2 register.

Entry into STR (ACPI S3) is initiated by the Operating System (OS), based on detecting a lack of system activity. The OS unloads all system device drivers as part of the process of entering STR. The OS then writes to the PM1_CNT I/O register in the ICH2 to trigger the transition into STR.

18	Intel® 82845 MCH for SDR Datasheet

Image 18

Intel 845 manual System Interrupts, Powerdown Flow

Contents

Intel 845 Chipset 82845 Memory Controller Hub MCH for SDR Document Number Intel 82845 MCH for SDR Datasheet Contents Register Device PMBASE1-Prefetchable Memory Base Address SMLT1-Secondary Master Latency Timer Register DeviceSystem Management Mode SMM Memory Range 103 PMLIMIT1-Prefetchable Memory Limit Address 117 114115 118 Tables Revision History Revision Description Date Intel 82845 MCH Features System Block Diagram Terminology and Notations General TerminologyTerm Description Data Type Size Data Type NotationNumber Format Notation Number Format Notation Example Reference Documents Document Intel 845 Chipset System Architecture Intel 82845 MCH Overview System Bus Error Checking System Bus Interface Memory Capacity System Memory InterfaceAGP Interface Technology SDR PC133 Intel MCH Clock Ratio Table Hub InterfaceIntel MCH Clocking Interface Speed Processor Bclk Powerdown Flow System Interrupts Signal Description Intel MCH Simplified Block Diagram DBIx# Data Bits System Bus SignalsSignal Name Type Description Strobe Address Bits Strobe Data Bits RS20 Response Type SDR Sdram Interface Signals Hub Interface SignalsSdram Column Address Strobe SCAS# is used with SRAS# During SBA Operation Not Used AGP Interface SignalsAGP Addressing Signals During FRAME# Operation Not Used RBF# AGP Flow Control SignalsAGP Status Signals WBF# AGP Strobes Signals 5 AGP/PCI Signals Command/Byte Enable Parity BCLK# Cmos Clocks, Reset, and Miscellaneous SignalsBclk RSTIN# Voltage Reference and Power Signals AGTL+ Bus Termination Voltage Inputs These pins provideSystem Memory Rcomp State Reset States During ResetSignal Name System Bus Interface Register Description Register Terminology PCI Bus Configuration Space Access Intel MCH Internal Device AssignmentsMCH Function Bus 0, Device # Standard PCI Bus Configuration Mechanism Routing Configuration Accesses CONFADDR-Configuration Address Register I/O Mapped Registers Configuration Enable Cfge Bit Descriptions Memory-Mapped Register Space CONFDATA-Configuration Data RegisterAddress 0CFCh Default Value 00000000h Access Size Bits Memory-mapped Register Address Map Address Offset 2Ch Default Value 00h Access Size Bits DRAMWIDTH-DRAM Width RegisterRow Parameters SDR Clocks Affected DQCMDSTR-Strength Control Register SDQ and CMD Signal Groups CKESTR-Strength Control Register Scke Signal Group Memory Address Offset 31h Default Value 00h Access Size Bits CSBSTR-Strength Control Register SCS# Signal Group Memory Address Offset 32h Default Value 00h Access Size Bits CKSTR-Strength Control Register Clock Signal Group Memory Address Offset 33h Default Value 00h Access Size Bits RCVENSTR-Strength Control Register Rcvenout Signal Group Memory Address Offset 34h Default Value 00h Access Size Bits Host-Hub Interface Bridge Device Registers Device Intel MCH Configuration Space DeviceAddress Register Register Name Default Access Value Smram EAPFdhc Esmramc Bit Description VID-Vendor Identification Register DeviceDID-Device Identification Register Device Bit Description PCICMD-PCI Command Register Device Address Offset 04-05h Default 0006h Access Size Bits Address Offset 06-07h Default Value 0090h Access PCISTS-PCI Status Register DeviceSize Bits RID-Revision Identification Register Device Address Offset 0Ah Default Value 00h Access Size BitsAddress Offset 0Bh Default Value 06h Access Size Bits SUBC-Sub-Class Code Register Device Address Offset 0Eh Default 00h Access Size Bits MLT-Master Latency Timer Register DeviceAddress Offset 0Dh Default Value 00h Access Size Bits Bit Description Hardwired to 00h. Writes have no effect APBASE-Aperture Base Configuration Register Device Offset 10-13h Default 00000008h Access Size Bits SVID-Subsystem Vendor Identification Device SID-Subsystem Identification DeviceCAPPTR-Capabilities Pointer Device Offset 60-67h DRB0-DRB7 Default 00h Access Size Bits AGPM-AGP Miscellaneous Configuration Register DeviceAddress Offset 51h Default Value 00h Access Size Bits 15 DRB07-DRAM Row Boundary Registers Device Offset 70-73h DRA0-DRA3 Default 00h Access Size Bits DRA-DRAM Row Attribute Registers Device Corresponding row Offset 78-7Bh Default 00000010h Access Size Bits DRT-DRAM Timing Register Device DRC-DRAM Controller Mode Register Device Offset 7C-7Fh Default 00000000h Access Size Bits = Normal operation DERRSYN-DRAM Error Syndrome Register Device EAP-Error Address Pointer Register DeviceAddress Offset 86h Default Value 00h Access Size Bits 21 PAM06-Programmable Attribute Map Registers Device Bits 7 Bits 6 Bits 5 Bits 4 Description PAM Register Attributes PAM6 PAM5 PAM4 PAM3 PAM2 PAM1 PAM0 DOS Application Area 00000h-9FFFh PAM Reg Attribute Bits Memory Segment Comments Offset Address Offset 97h Default Value 00h Access Size Bits FDHC-Fixed Dram Hole Control Register Device Global Smram Enable GSMRAME-R/W/L SMRAM-System Management RAM Control Register Device SMRAML2EN SML2-RO. Hardwired to SMRAMCache SMCACHE-RO. Hardwired toSMRAML1EN SML1-RO. Hardwired to ESMRAMC-Extended System Mgmt RAM Control Register Device ACAPID-AGP Capability Identifier Register Device AGPSTAT-AGP Status Register Device This register reports AGP device capability/status AGP Enable Agpen AGPCMD-AGP Command Register DeviceSideBand Address Enable Sbaen Fast Write Enable Fwen AGPCTRL-AGP Control Register Device Data Rate 4x Override Address Offset B4h Default Value 00h Access Size Bits APSIZE-Aperture Size DeviceAperture Size ATTBASE-Aperture Translation Table Base Register Device AMTT-AGP Interface Multi-Transaction Timer Register Device Address Offset BCh Default Value 00h Access Size Bits LPTT-AGP Low Priority Transaction Timer Register Device Address Offset BDh Default Value 00h Access Size Bits Address Offset C4-C5h Default Value 0100h Access Size Bits TOM-Top of Low Memory Register Device MCHCFG-MCH Configuration Register Device Offset C6-C7h Default 0000h Access Size BitsApic Memory Range Disable APICDIS-R/W ERRSTS-Error Status Register Device Address Offset C8-C9h Default Value 0000h Access Size Bits Single-bit Dram ECC Error Flag Dserr ERRCMD-Error Command Register DeviceAddress Offset CA-CBh Default Value 0000h Access Size Bits Serr on Non-DRAM Lock Lckerr Serr Multiple-Bit Dram ECC Error Dmerrserr Serr on AGP Access Outside of Graphics Aperture OogfserrSerr on Invalid AGP Access Iaafserr Serr on Single-bit ECC Error Dserr Address Offset CC-CDh Default Value 0000h Access Size Bits SMICMD-SMI Command Register DeviceSCICMD-SCI Command Register Device Address Offset CE-CDh Default Value 0000h Access Size Bits Address Offset DE-DFh Default Value 0000h Access Size Bits Address Offset E4h Default Value 0104A009h Access Size BitsSKPD-Scratchpad Data Register Device Address Symbol Name Default Access Bridge Registers Device 1 VID1-Vendor Identification Register Device 2 DID1-Device Identification Register DeviceDrtc Parity Error Enable PERRE1-RO. Not Implemented Hardwired to PCICMD1-PCI-PCI Command Register DeviceAddress Offset 04-05h Default 0000h Access Memory Access Enable MAE1-R/W Signaled System Error SSE1-R/WC Address Offset 06-07h Default Value 00A0h AccessDetected Parity Error DPE1-RO. Not Implemented Hardwired to PCISTS1-PCI-PCI Status Register Device SUBC1-Sub-Class Code Register Device Address Offset 0Ah Default Value 04h Access Size Bits5 RID1-Revision Identification Register Device 7 BCC1-Base Class Code Register Device Offset 18h Default 00h Access Size Bits 8 MLT1-Master Latency Timer Register DeviceOffset 0Eh Default 01h Access Size Bits 9 HDR1-Header Type Register Device SBUSN1-Secondary Bus Number Register Device Offset 19h Default 00h Access Size BitsOffset 1Ah Default 00h Access Size Bits SUBUSN1-Subordinate Bus Number Register Device SMLT1-Secondary Master Latency Timer Register Device Address Offset 1Bh Default Value 00h Access Size Bits IOBASE1-I/O Base Address Register Device IOLIMIT1-I/O Limit Address Register Device SSTS1-Secondary PCI-PCI Status Register Device Address Offset 1E-1Fh Default Value 02A0h AccessDetected Parity Error DPE1-R/WC Received Master Abort Status RMAS1-R/WC MBASE1-Memory Base Address Register Device Address Offset 20-21h Default Value FFF0h Access Size BitsAddress Offset 22-23h Default Value 0000h Access Size Bits MLIMIT1-Memory Limit Address Register Device PMBASE1-Prefetchable Memory Base Address Register Device Address Offset 24-25h Default Value FFF0h Access Size BitsAddress Offset 26-27h Default Value 0000h Access Size Bits PMLIMIT1-Prefetchable Memory Limit Address Register Device Address Offset 3Eh Default 00h Access BCTRL1-PCI-PCI Bridge Control Register Device ERRCMD1-Error Command Register Device Address Offset 40h Default Value 00h Access Size BitsSerr on Receiving Target Abort Serta Address Offset 50-57h Default Value 00h Access Size Bits Write Thermal Management Mode WTMModeDWTC-DRAM Write Thermal Management Control Register Device Read Thermal Management Mode RTMMode DRTC-DRAM Read Thermal Management Control Register Device This page is intentionally left blank Memory Address Ranges Addressable Memory Space DOS Compatible Area Address Map VGA and MDA Memory Space Vgab PAM Memory Spaces ISA Hole Memory Space System Bus Interrupt Apic Memory Space Tseg SMM Memory SpaceIoapic Memory Space High SMM Memory Space AGP Memory and Prefetchable Memory AGP Memory Address RangesAGP Aperture Space Device 0 BAR Hub Interface Subtractive Decode System Management Mode SMM Memory Range AGP Dram Graphics Aperture SMM Space Address Ranges SMM Space DefinitionSMM Space Restrictions Tseg I/O Address Space Intel MCH Decode Rules and Cross-Bridge Address MappingHub Interface Decode Rules Cycles Initiated Using AGP FRAME# Protocol AGP Interface Decode Rules System Bus Dynamic Bus InversionDBI30# System Bus Interrupt Delivery Upstream Interrupt Messages System Memory Interface Memory Organization and ConfigurationSupported Dimm Configurations Single Data Rate SDR Sdram Interface Overview Data Bytes on Dimm Used for Programming Dram Registers Byte Function Memory Address Translation and Decoding Address Translation and Decoding AGP Interface Overview Dram Performance DescriptionAGP Target Operations BE30# MCH Host Bridge Command Encoding Response as PCIx Target 4 4x AGP Protocol AGP Signal LevelsAGP Transaction Ordering Fast Writes PCI Command BE30# Intel MCH Encoding AGP FRAME# Transactions on AGPData Rate Control Bits 116 Power and Thermal Management Processor Power State Control Intel MCH System Reset and Power Sequencing Intel MCH ClockingSleep State Control Absolute Maximum Ratings Power CharacteristicsPower Characteristics Absolute Maximum Ratings Signal Groups Signal GroupsSignal Signal Type Signals BCLK, BCLK# DC Characteristics DC Characteristics Intel 82845 MCH for SDR Datasheet 123 124 Ballout and Package Information Intel 82845 MCH Ballout Diagram Top View-Left Side Intel 82845 MCH Ballout Diagram Top View-Right Side Signal Name Ball # AB5 HADSTB0# HADSTB1#AA2 AA5 130 SBA6 SBA4SBA5 SBA7 132 VSSA1 VSSA0 Intel MCH FC-BGA Package Dimensions Top and Side View Package Mechanical Information Intel MCH FC-BGA Package Dimensions Bottom View 136 XOR Test Mode Initialization XOR Tree Chain XOR Chain Chain 0 Ball Element # Signal Name Initial LogicXOR Chains AE6 HDSTBP1# SCK10 Chain 1 Ball Element # Signal Name Initial Logic Chain 2 Ball Element # Signal Name Initial Logic Level SDQ22SDQ65 Chain 3 Ball Element # Signal Name Initial Logic Level SBCS1SDQ64 Chain 4 Ball Element # Signal Name Initial Logic Level Adstb Chain 5 Ball Element # Signal Name Initial Logic Level Gado Intel 82845 MCH for SDR Datasheet 145 Chain 6 Ball Element # Signal Name Initial Logic Level AH9 DBI2# AD5 DBI0# Chain 7 Ball Element # SDR Ball name Initial Logic LevelAE6 HDSTBN1# AD4 HDSTBN0# 148