Intel 845 manual Bridge Registers Device, Address Symbol Name Default Access

Register Description

R

3.6Bridge Registers (Device 1)

Table 10. provides the register address map for Device 0 PCI configuration space. An “s” in the Default Value column indicates that a strap determines the power-up default value for that bit.

Table 10. Intel® MCH Configuration Space (Device 1)

Address	Symbol	Name	Default	Access
Offset
00-01h	VID1	Vendor Identification	8086h	RO
02–03h	DID1	Device Identification	1A31h	RO
04–05h	PCICMD1	PCI Command	0000h	RO, R/W
06–07h	PCISTS1	PCI Status	00A0h	RO, R/WC
08	RID1	Revision Identification	03h, 04h	RO
09	—	Reserved	—	—
0Ah	SUBC1	Sub-Class Code	04h	RO
0Bh	BCC1	Base Class Code	06h	RO
0Ch	—	Reserved	—	—
0Dh	MLT1	Master Latency Timer	00h	R/W
0Eh	HDR1	Header Type	01h	RO
0F–17h	—	Reserved	—	—
18h	PBUSN1	Primary Bus Number	00h	RO
19h	SBUSN1	Secondary Bus Number	00h	R/W
1Ah	SUBUSN1	Subordinate Bus Number	00h	R/W
1Bh	SMLT1	Secondary Bus Master Latency Timer	00h	R/W
1Ch	IOBASE1	I/O Base Address	F0h	R/W
1Dh	IOLIMIT1	I/O Limit Address	00h	R/W
1E–1Fh	SSTS1	Secondary Status	02A0h	RO, R/WC
20–21h	MBASE1	Memory Base Address	FFF0h	R/W
22–23h	MLIMIT1	Memory Limit Address	0000h	R/W
24–25h	PMBASE1	Prefetchable Memory Base Address	FFF0h	R/W
26–27h	PMLIMIT1	Prefetchable Memory Limit Address	0000h	R/W
28–3Dh	—	Reserved	—	—
3Eh	BCTRL1	Bridge Control	00h	RO, R/W
3Fh	—	Reserved	—	—
40h	ERRCMD1	Error Command	00h	R/W
41–4Fh	—	Reserved	—	—
50–57h	DWTC	DRAM Write Thermal Management Control	0000000	R/W/L
			0h

80 Intel® 82845 MCH for SDR Datasheet