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845 manual
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148 pages, 1.09 Mb
Intel
®
845 Chipset: 82845
Memory Controller Hub (MCH)
for SDR
Datasheet
January 2002
Document Number:
290725-002
R
Contents
Main
Intel 845 Chipset: 82845 Memory Controller Hub (MCH) for SDR
Page
Contents
Page
Page
Page
Figures
Tables
Revision History
Intel 82845 MCH Features
10 Intel 82845 MCH for SDR Datasheet
System Block Diagram
1 Introduction
1.1 Terminology and Notations
Page
1.2 Reference Documents
1.3 Intel 845 Chipset System Architecture
Intel 82801BA I/O Controller Hub 2 (ICH2)
1.4 Intel 82845 MCH Overview
1.4.1 System Bus Interface
1.4.2 System Bus Error Checking
1.4.3 System Memory Interface
1.4.4 AGP Interface
1.4.5 Hub Interface
1.4.6 Intel MCH Clocking
1.4.7 System Interrupts
1.4.8 Powerdown Flow
2 Signal Description
Signal Description
20 Intel 82845 MCH for SDR Datasheet
Figure 1. Intel MCH Simplified Block Diagram
2.1 System Bus Signals
Page
2.2 SDR SDRAM Interface Signals
2.3 Hub Interface Signals
2.4 AGP Interface Signals
2.4.1 AGP Addressing Signals
2.4.2 AGP Flow Control Signal s
2.4.3 AGP Status Signals
Signal Description
26 Intel 82845 MCH for SDR Datasheet
2.4.4 AGP Strobes Signals
2.4.5 AGP/PCI Signals
Page
2.5 Clocks, Reset, and Miscellaneous Signals
2.6 Voltage Reference and Power Signals
Signal Description
30 Intel 82845 MCH for SDR Datasheet
2.7 Reset States During Reset
3 Register Description
3.1 Register Terminology
3.2 PCI Bus Configuration Space Access
3.2.1 Standard PCI Bus Configuration Mechanism
3.2.2 Routing Configuration Accesses
PCI Bus 0 Configuration Mechanism
Primary PCI and Downstream Configuration Mechanism
AGP Configuration Mechanism
3.3 I/O Mapped Registers
3.3.1 CONF_ADDRConfiguration Address Register
Page
3.3.2 CONF_DATAConfiguration Data Register
3.4 Memory-Mapped Register Space
3.4.1 DRAMWIDTHDRAM Width Register
3.4.2 DQCMDSTRStrength Control Register (SDQ and CMD Signal Groups)
3.4.3 CKESTRStrength Control Register (SCKE Signal Group)
3.4.4 CSBSTRStrength Control Register (SCS# Si gnal Group)
3.4.5 CKSTRStrength Control Register (Cl ock Si gnal Group)
3.4.6 RCVENSTRStrength Control Register (RCVENOUT Signal Group)
Register Description
Intel 82845 MCH for SDR Datasheet 43
3.5 Host-Hub Interface Bridge Device Registers (Device 0)
Page
3.5.1 VIDVendor Identificati on Regi ster (Device 0)
3.5.2 DIDDevice Identification Register (Device 0)
3.5.3 PCICMDPCI Command Register (Device 0)
3.5.4 PCISTSPCI Status Register (Device 0)
3.5.5 RIDRevision Identification Register (Device 0)
3.5.6 SUBCSub-Class Code Register (Device 0)
3.5.7 BCCBase Class Code Register (Device 0)
3.5.8 MLTMaster Latency Timer Register (Device 0)
3.5.9 HDRHeader Type Register (Device 0)
3.5.10 APBASEAperture Base Configuration Register (Device 0)
3.5.11 SVIDSubsystem Vendor Identification (Device 0)
3.5.12 SIDSubsystem Identification (Device 0)
3.5.13 CAPPTRCapabilities Pointer (Device 0)
3.5.14 AGPMAGP Miscellaneous Configurati on Regi ster (Device 0)
3.5.15 DRB[0:7]DRAM Row Boundary Registers (Device 0)
3.5.16 DRADRAM Row Attribute Registers (Device 0)
Page
3.5.17 DRTDRAM Timing Register (Device 0)
3.5.18 DRCDRAM Controller Mode Register (Device 0)
Page
3.5.19 DERRSYNDRAM Error Syndrome Register (Device 0)
3.5.20 EAPError Address Pointer Register (Device 0)
3.5.21 PAM[0:6]Programmable Attribute Map Registers (Device 0)
Page
DOS Application Area (00000h9FFFh)
Video Buffer Area (A0000hBFFFFh)
Expansion Area (C0000hDFFFFh)
Extended System BIOS Area (E0000hEFFFFh)
System BIOS Area (F0000hFFFFFh)
3.5.22 FDHCFixed DRAM Hole Contr ol Regi ster (Device 0)
3.5.23 SMRAMSystem Management RAM Control Register (Device 0)
3.5.24 ESMRAMCExtended System Mgmt RAM Control Register (Device 0)
3.5.25 ACAPIDAGP Capability Identifier Register (Device 0)
3.5.26 AGPSTATAGP Status Register (Device 0)
3.5.27 AGPCMDAGP Command Register (Device 0)
3.5.28 AGPCTRLAGP Control Register (Device 0)
3.5.29 APSIZEAperture Size (Device 0)
3.5.30 ATTBASEAperture Translation Table Base Register (Device 0)
3.5.31 AMTTAGP Interface Multi-Transaction Timer Register (Device 0)
3.5.32 LPTTAGP Low Priority Transaction Timer Register (Device 0)
3.5.33 TOMTop of Low Memory Register (Device 0)
3.5.34 MCHCFGMCH Configuration Register (Device 0)
3.5.35 ERRSTSError Status Register (Device 0)
3.5.36 ERRCMDError Command Register (Device 0)
Page
3.5.37 SMICMDSMI Command Register (Device 0)
3.5.38 SCICMDSCI Command Register (Device 0)
3.5.39 SKPDScratchpad Data Register (Device 0)
3.5.40 CAPIDProduct Specific Capability Identifier Register (Device 0)
3.6 Bridge Registers (Device 1)
3.6.1 VID1Vendor Identificati on Regi ster (Device 1)
3.6.2 DID1Device Identification Register (Device 1)
3.6.3 PCICMD1PCI-PCI Command Register (Device 1)
3.6.4 PCISTS1PCI-PCI Status Register (Device 1)
3.6.5 RID1Revision Identification Register (Device 1)
3.6.6 SUBC1Sub-Class Code Register (Device 1)
3.6.7 BCC1Base Class Code Register (Device 1)
3.6.8 MLT1Master Latency Timer Register (Device 1)
3.6.9 HDR1Header Type Register (Device 1)
3.6.10 PBUSN1Primary Bus Number Register (Device 1)
3.6.11 SBUSN1Secondary Bus Number Register (Device 1)
3.6.12 SUBUSN1Subordi nate Bus Number Register (Device 1)
3.6.13 SMLT1Secondary Master Latency Timer Register (Device 1)
3.6.14 IOBASE1I/O Base Address Register (Device 1)
3.6.15 IOLIMIT1I/O Limit Address Register (Device 1)
3.6.16 SSTS1Secondary PCI-PCI Status Register (Device 1)
3.6.17 MBASE1Memory Base Address Register (Device 1)
3.6.18 MLIM IT1Memory Limit Address Register (Device 1)
3.6.19 PMBASE1Prefetchable Memory Base Address Register (Device 1)
3.6.20 PMLIMIT1Prefetchable Memory Limit Address Register (Device 1)
3.6.21 BCTRL1PCI-PCI Bridge Control Register (Device 1)
3.6.22 ERRCMD1Error Command Register (Device 1)
3.6.23 DWTCDRAM Write Ther mal Management Control Register (Device 1)
3.6.24 DRTCDRAM Read Thermal Management Control Register (Device 1)
Page
4 System Address Map
4.1 Memory Address Ranges
System Address Map
98 Intel 82845 MCH for SDR Datasheet
Figure 4. DOS Compatible Area Address Map
4.1.1 VGA and MDA Memory Space
4.1.2 PAM Memory Spaces
4.1.3 ISA Hole Memory Space
4.1.4 TSEG SMM Memory Space
4.1.5 IOAPIC Memory Space
4.1.6 System Bus Interrupt APIC Memory Space
4.1.7 High SMM Memory Space
4.1.8 AGP Aperture Space (Device 0 BAR)
4.2 AGP Memory Address Ranges
4.2.1 AGP DRAM Graphics Aperture
4.3 System Management Mode (SMM) Memory Range
4.3.1 SMM Space Definition
4.3.2 SMM Space Restrictions
4.4 I/O Address Space
4.5 Intel MCH Decode Rules and Cross-Bridge Address Mapping
4.5.1 Hub Interface Decode Rules
4.5.2 AGP Interface Decode Rules
Cycles Initiated Using AGP FRAME# Protocol
Cycles Initiated Using AGP PIPE# or SB Protocol
AGP Accesses to MCH that Cross Device Boundaries
5 Functional Description
5.1 System Bus
5.1.1 Dynamic Bus Inversion
5.1.2 System Bus Interrupt Delivery
5.1.3 Upstream Interrupt Messages
5.2 System Memory Interface
5.2.1 Single Data Rate (SDR) SDRAM Interface Overview
5.2.2 Memory Organization and Configur ation
5.2.2.1 Configuration Mechanism For DIMMs
Memory Detection and Initialization
SMBus Configuration and Access of the Serial Presence Detect Ports
Memory Register Programming
5.2.3 Memory Address Translation and Decoding
5.2.4 DRAM Performance Description
5.2.4.1 Data Integrity (ECC)
5.3 AGP Interface Overview
5.3.1 AGP Target Operations
Page
5.3.2 AGP Transaction Ordering
5.3.3 AGP Signal Levels
5.3.4 4x AGP Protocol
5.3.5 Fast Writes
5.3.6 AGP FRAME# Transactions on AGP
MCH Initiator and Target Operations
Page
MCH Retry/Disconnect Conditions
Delayed Transaction
5.4 Power and Thermal Management
5.4.1 Processor Power State Control
5.4.2 Sleep State Control
5.5 Intel MCH Clocking
5.6 Intel MCH System Reset and Power Sequencing
6 Electrical Characteristics
6.1 Absolute Maximum Ratings
6.2 Power Characteristics
6.3 Signal Groups
Page
Electrical Characteristics
122 Intel 82845 MCH for SDR Datasheet
6.4 DC Characteristics
Table 21. DC Characteristics
Electrical Characteristics
Intel 82845 MCH for SDR Datasheet 123
Page
7 Ballout and Package Information
Ballout and Package Information
126 Intel 82845 MCH for SDR Datasheet
Figure 6. Intel 82845 MCH Ballout Diagram (Top ViewLeft Side)
Ballout and Package Information
Intel 82845 MCH for SDR Datasheet 127
Figure 7. Intel 82845 MCH Ballout Diagram (Top ViewRight Side)
Ballout and Package Information
128 Intel 82845 MCH for SDR Datasheet
Table 22. Intel 82845 MCH Ballout Listed Alphabetically by Signal Name
Page
Page
Page
Page
Page
7.1 Package Mechanical Information
Ballout and Package Information
Intel 82845 MCH for SDR Datasheet 135
Figure 9. Intel MCH FC-BGA Package Dimensions (Bottom View)
Page
8 Testability
8.1 XOR Test Mode Initialization
8.2 XOR Chains
Page
Testability
140 Intel 82845 MCH for SDR Datasheet
Table 24. XOR Chain 1
Testability
Intel 82845 MCH for SDR Datasheet 141
Table 25. XOR Chain 2
Testability
142 Intel 82845 MCH for SDR Datasheet
Table 26. XOR Chain 3
Testability
Intel 82845 MCH for SDR Datasheet 143
Table 27. XOR Chain 4
Testability
144 Intel 82845 MCH for SDR Datasheet
Table 28. XOR Chain 5
Page
Testability
146 Intel 82845 MCH for SDR Datasheet
Table 29. XOR Chain 6
Testability
Intel 82845 MCH for SDR Datasheet 147
Table 30. XOR Chain 7