Intel 845 manual Standard PCI Bus Configuration Mechanism, Routing Configuration Accesses

Register Description

R

3.2.1Standard PCI Bus Configuration Mechanism

The PCI Bus defines a slot based "configuration space" that allows each device to contain up to 8 functions with each function containing up to 256 8-bit configuration registers. The PCI specification defines two bus cycles to access the PCI configuration space: Configuration Read and Configuration Write. Memory and I/O spaces are supported directly by the processor. Configuration space is supported by a mapping mechanism implemented within the MCH. The PCI specification defines two mechanisms to access configuration space, Mechanism #1 and Mechanism #2. The MCH supports only Mechanism #1.

The configuration access mechanism makes use of the CONF_ADDR Register (at I/O address 0CF8h though 0CFBh) and CONF_DATA register (at I/O address 0CFCh though 0CFFh). To reference a configuration register a DWord I/O write cycle is used to place a value into CONF_ADDR that specifies the PCI bus, the device on that bus, the function within the device, and a specific configuration register of the device function being accessed. CONF_ADDR[31] must be 1 to enable a configuration cycle. CONF_DATA then becomes a window into the four bytes of configuration space specified by the contents of CONF_ADDR. Any read or write to CONF_DATA results in the MCH translating the CONF_ADDR into the appropriate configuration cycle.

The MCH is responsible for translating and routing the processor’s I/O accesses to the

CONF_ADDR and CONF_DATA registers to internal MCH configuration registers, hub interface or AGP.

3.2.2Routing Configuration Accesses

The MCH supports two bus interfaces: the hub interface and AGP. PCI configuration cycles are selectively routed to one of these interfaces. The MCH is responsible for routing PCI configuration cycles to the proper interface. PCI configuration cycles to the ICH2 internal devices and Primary PCI (including downstream devices) are routed to the ICH2 via the hub interface. AGP configuration cycles are routed to AGP. The AGP interface is treated as a separate PCI bus from the configuration point of view. Routing of configuration AGP is controlled via the standard PCI- PCI bridge mechanism using information contained within the Primary Bus Number, the Secondary Bus Number, and the Subordinate Bus Number registers of the corresponding PCI-PCI bridge device.

A detailed description of the mechanism for translating processor I/O bus cycles to configuration cycles on one of the buses is described below.

PCI Bus 0 Configuration Mechanism

The MCH decodes the Bus Number (bits 23:16) and the Device Number fields of the

CONF_ADDR register. If the Bus Number field of CONF_ADDR is 0, the configuration cycle is targeting a PCI Bus 0 device.

•The Host-HI Bridge entity in the MCH is hardwired as Device 0 on PCI Bus 0.

•The Host-AGP Bridge entity in the MCH is hardwired as Device 1 on PCI Bus 0.

Configuration cycles to any of the MCH’s internal devices are confined to the MCH and not sent over the hub interface. Accesses to disabled MCH internal devices are forwarded over the hub interface as Type 0 Configuration Cycles.

Intel® 82845 MCH for SDR Datasheet 33