
Register Description
R
3.6.5RID1—Revision Identification Register (Device 1)
Address Offset: | 08h |
Default Value: | See RID1 table below |
Access: | RO |
Size: | 8 bits |
This register contains the revision number of the MCH device 1. These bits are read only and writes to this register have no effect.
Bit | Description |
|
|
7:0 | Revision Identification Number (RID): This is an |
| identification number for the MCH device 1. |
| 03h = A3 Stepping |
| 04h = B0 Stepping |
|
|
3.6.6SUBC1—Sub-Class Code Register (Device 1)
Address Offset: | 0Ah |
Default Value: | 04h |
Access: | RO |
Size: | 8 bits |
This register contains the
Bit | Description |
|
|
7:0 | |
| MCH. |
| 04h = Host bridge. |
|
|
3.6.7BCC1—Base Class Code Register (Device 1)
Address Offset: | 0Bh |
Default Value: | 06h |
Access: | RO |
Size: | 8 bits |
This register contains the Base Class Code of the MCH device 1.
Bit | Description |
|
|
7:0 | Base Class Code (BASEC): This is an |
| MCH device 1. |
| 06h = Bridge device. |
|
|
84 | Intel® 82845 MCH for SDR Datasheet |