System Bus, Dynamic Bus Inversion, DBI30# | Intel 845 specification

Functional Description

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5 Functional Description

This chapter describes the system bus that connects the MCH to the processor, the system memory interface, the AGP interface, the MCH power and thermal management, the MCH clocking, and the MCH system reset and power sequencing.

5.1System Bus

The MCH supports the Pentium 4 processor subset of the Enhanced Mode Scaleable Bus. Source synchronous transfers are used for the address and data signals. The address signals are double pumped and a new address can be generated every other bus clock. At 100 MHz bus frequency, the address signals run at 200 MT/s for a maximum address queue rate of 50 M addresses/sec. The data is quad pumped and an entire 64-byte cache line can be transferred in two bus clocks. At

100 MHz bus frequency, the data signals run at 400 MT/s for a maximum bandwidth of 3.2 GB/s. The MCH supports a 12 deep IOQ.

The MCH supports two outstanding deferred transactions on the system bus. The two transactions must target different I/O interfaces as only one deferred transaction can be outstanding to any single I/O interface at a time.

5.1.1Dynamic Bus Inversion

The MCH supports Dynamic Bus Inversion (DBI) when driving and receiving data from the system bus. DBI limits the number of data signals that are driven to a low voltage on each quad pumped data phase. This decreases the power consumption of the MCH. DBI[3:0]# indicates if the corresponding 16 bits of data are inverted on the bus for each quad pumped data phase:

DBI[3:0]#

Data Bits

DBI0# HD[15:0]#

DBI1# HD[31:16]#

DBI2# HD[47:32]#

DBI3# HD[63:48]#

When the processor or the MCH drives data, each 16-bit segment is analyzed. If more than 8 of the 16 signals would normally be driven low on the bus, the corresponding DBI# signal will be asserted and the data will be inverted prior to being driven on the bus. When the processor or the MCH receives data, it monitors DBI[3:0]# to determine if the corresponding data segment should be inverted.

Intel® 82845 MCH for SDR Datasheet

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Image 107

Intel 845 manual System Bus, Dynamic Bus Inversion, DBI30#

Contents

Document Number Intel 845 Chipset 82845 Memory Controller Hub MCH for SDR Intel 82845 MCH for SDR Datasheet Contents Register Device PMLIMIT1-Prefetchable Memory Limit Address SMLT1-Secondary Master Latency Timer Register DeviceSystem Management Mode SMM Memory Range 103 PMBASE1-Prefetchable Memory Base Address 118 114115 117 Tables Revision Description Date Revision History Intel 82845 MCH Features System Block Diagram Term Description Terminology and NotationsGeneral Terminology Number Format Notation Example Data Type NotationNumber Format Notation Data Type Size Document Reference Documents Intel 82845 MCH Overview Intel 845 Chipset System Architecture System Bus Interface System Bus Error Checking Technology SDR PC133 System Memory InterfaceAGP Interface Memory Capacity Interface Speed Processor Bclk Hub InterfaceIntel MCH Clocking Intel MCH Clock Ratio Table System Interrupts Powerdown Flow Signal Description Intel MCH Simplified Block Diagram Strobe Address Bits System Bus SignalsSignal Name Type Description DBIx# Data Bits RS20 Response Type Strobe Data Bits Sdram Column Address Strobe SCAS# is used with SRAS# SDR Sdram Interface SignalsHub Interface Signals During FRAME# Operation Not Used AGP Interface SignalsAGP Addressing Signals During SBA Operation Not Used WBF# AGP Flow Control SignalsAGP Status Signals RBF# 5 AGP/PCI Signals AGP Strobes Signals Parity Command/Byte Enable RSTIN# Clocks, Reset, and Miscellaneous SignalsBclk BCLK# Cmos System Memory Rcomp Voltage Reference and Power SignalsAGTL+ Bus Termination Voltage Inputs These pins provide System Bus Interface Reset States During ResetSignal Name State Register Terminology Register Description MCH Function Bus 0, Device # PCI Bus Configuration Space AccessIntel MCH Internal Device Assignments Routing Configuration Accesses Standard PCI Bus Configuration Mechanism I/O Mapped Registers CONFADDR-Configuration Address Register Bit Descriptions Configuration Enable Cfge Memory-mapped Register Address Map CONFDATA-Configuration Data RegisterAddress 0CFCh Default Value 00000000h Access Size Bits Memory-Mapped Register Space Row Parameters SDR Clocks Affected Address Offset 2Ch Default Value 00h Access Size BitsDRAMWIDTH-DRAM Width Register DQCMDSTR-Strength Control Register SDQ and CMD Signal Groups Memory Address Offset 31h Default Value 00h Access Size Bits CKESTR-Strength Control Register Scke Signal Group Memory Address Offset 32h Default Value 00h Access Size Bits CSBSTR-Strength Control Register SCS# Signal Group Memory Address Offset 33h Default Value 00h Access Size Bits CKSTR-Strength Control Register Clock Signal Group Memory Address Offset 34h Default Value 00h Access Size Bits RCVENSTR-Strength Control Register Rcvenout Signal Group Value Intel MCH Configuration Space DeviceAddress Register Register Name Default Access Host-Hub Interface Bridge Device Registers Device Esmramc EAPFdhc Smram Bit Description VID-Vendor Identification Register DeviceDID-Device Identification Register Device Bit Description Address Offset 04-05h Default 0006h Access Size Bits PCICMD-PCI Command Register Device Size Bits Address Offset 06-07h Default Value 0090h AccessPCISTS-PCI Status Register Device SUBC-Sub-Class Code Register Device Address Offset 0Ah Default Value 00h Access Size BitsAddress Offset 0Bh Default Value 06h Access Size Bits RID-Revision Identification Register Device Bit Description Hardwired to 00h. Writes have no effect MLT-Master Latency Timer Register DeviceAddress Offset 0Dh Default Value 00h Access Size Bits Address Offset 0Eh Default 00h Access Size Bits Offset 10-13h Default 00000008h Access Size Bits APBASE-Aperture Base Configuration Register Device CAPPTR-Capabilities Pointer Device SVID-Subsystem Vendor Identification DeviceSID-Subsystem Identification Device 15 DRB07-DRAM Row Boundary Registers Device AGPM-AGP Miscellaneous Configuration Register DeviceAddress Offset 51h Default Value 00h Access Size Bits Offset 60-67h DRB0-DRB7 Default 00h Access Size Bits DRA-DRAM Row Attribute Registers Device Offset 70-73h DRA0-DRA3 Default 00h Access Size Bits Corresponding row DRT-DRAM Timing Register Device Offset 78-7Bh Default 00000010h Access Size Bits Offset 7C-7Fh Default 00000000h Access Size Bits DRC-DRAM Controller Mode Register Device = Normal operation Address Offset 86h Default Value 00h Access Size Bits DERRSYN-DRAM Error Syndrome Register DeviceEAP-Error Address Pointer Register Device Bits 7 Bits 6 Bits 5 Bits 4 Description 21 PAM06-Programmable Attribute Map Registers Device PAM6 PAM5 PAM4 PAM3 PAM2 PAM1 PAM0 PAM Register Attributes PAM Reg Attribute Bits Memory Segment Comments Offset DOS Application Area 00000h-9FFFh FDHC-Fixed Dram Hole Control Register Device Address Offset 97h Default Value 00h Access Size Bits SMRAM-System Management RAM Control Register Device Global Smram Enable GSMRAME-R/W/L ESMRAMC-Extended System Mgmt RAM Control Register Device SMRAMCache SMCACHE-RO. Hardwired toSMRAML1EN SML1-RO. Hardwired to SMRAML2EN SML2-RO. Hardwired to ACAPID-AGP Capability Identifier Register Device This register reports AGP device capability/status AGPSTAT-AGP Status Register Device Fast Write Enable Fwen AGPCMD-AGP Command Register DeviceSideBand Address Enable Sbaen AGP Enable Agpen Data Rate 4x Override AGPCTRL-AGP Control Register Device Aperture Size Address Offset B4h Default Value 00h Access Size BitsAPSIZE-Aperture Size Device ATTBASE-Aperture Translation Table Base Register Device Address Offset BCh Default Value 00h Access Size Bits AMTT-AGP Interface Multi-Transaction Timer Register Device Address Offset BDh Default Value 00h Access Size Bits LPTT-AGP Low Priority Transaction Timer Register Device TOM-Top of Low Memory Register Device Address Offset C4-C5h Default Value 0100h Access Size Bits Apic Memory Range Disable APICDIS-R/W MCHCFG-MCH Configuration Register DeviceOffset C6-C7h Default 0000h Access Size Bits Address Offset C8-C9h Default Value 0000h Access Size Bits ERRSTS-Error Status Register Device Serr on Non-DRAM Lock Lckerr ERRCMD-Error Command Register DeviceAddress Offset CA-CBh Default Value 0000h Access Size Bits Single-bit Dram ECC Error Flag Dserr Serr on Single-bit ECC Error Dserr Serr on AGP Access Outside of Graphics Aperture OogfserrSerr on Invalid AGP Access Iaafserr Serr Multiple-Bit Dram ECC Error Dmerrserr Address Offset CE-CDh Default Value 0000h Access Size Bits SMICMD-SMI Command Register DeviceSCICMD-SCI Command Register Device Address Offset CC-CDh Default Value 0000h Access Size Bits SKPD-Scratchpad Data Register Device Address Offset DE-DFh Default Value 0000h Access Size BitsAddress Offset E4h Default Value 0104A009h Access Size Bits Bridge Registers Device Address Symbol Name Default Access Drtc 1 VID1-Vendor Identification Register Device2 DID1-Device Identification Register Device Memory Access Enable MAE1-R/W PCICMD1-PCI-PCI Command Register DeviceAddress Offset 04-05h Default 0000h Access Parity Error Enable PERRE1-RO. Not Implemented Hardwired to PCISTS1-PCI-PCI Status Register Device Address Offset 06-07h Default Value 00A0h AccessDetected Parity Error DPE1-RO. Not Implemented Hardwired to Signaled System Error SSE1-R/WC 7 BCC1-Base Class Code Register Device Address Offset 0Ah Default Value 04h Access Size Bits5 RID1-Revision Identification Register Device SUBC1-Sub-Class Code Register Device 9 HDR1-Header Type Register Device 8 MLT1-Master Latency Timer Register DeviceOffset 0Eh Default 01h Access Size Bits Offset 18h Default 00h Access Size Bits SUBUSN1-Subordinate Bus Number Register Device Offset 19h Default 00h Access Size BitsOffset 1Ah Default 00h Access Size Bits SBUSN1-Secondary Bus Number Register Device Address Offset 1Bh Default Value 00h Access Size Bits SMLT1-Secondary Master Latency Timer Register Device IOLIMIT1-I/O Limit Address Register Device IOBASE1-I/O Base Address Register Device Received Master Abort Status RMAS1-R/WC Address Offset 1E-1Fh Default Value 02A0h AccessDetected Parity Error DPE1-R/WC SSTS1-Secondary PCI-PCI Status Register Device MLIMIT1-Memory Limit Address Register Device Address Offset 20-21h Default Value FFF0h Access Size BitsAddress Offset 22-23h Default Value 0000h Access Size Bits MBASE1-Memory Base Address Register Device PMLIMIT1-Prefetchable Memory Limit Address Register Device Address Offset 24-25h Default Value FFF0h Access Size BitsAddress Offset 26-27h Default Value 0000h Access Size Bits PMBASE1-Prefetchable Memory Base Address Register Device BCTRL1-PCI-PCI Bridge Control Register Device Address Offset 3Eh Default 00h Access Serr on Receiving Target Abort Serta ERRCMD1-Error Command Register DeviceAddress Offset 40h Default Value 00h Access Size Bits DWTC-DRAM Write Thermal Management Control Register Device Address Offset 50-57h Default Value 00h Access Size BitsWrite Thermal Management Mode WTMMode DRTC-DRAM Read Thermal Management Control Register Device Read Thermal Management Mode RTMMode This page is intentionally left blank Addressable Memory Space Memory Address Ranges DOS Compatible Area Address Map Vgab VGA and MDA Memory Space ISA Hole Memory Space PAM Memory Spaces High SMM Memory Space Tseg SMM Memory SpaceIoapic Memory Space System Bus Interrupt Apic Memory Space Hub Interface Subtractive Decode AGP Memory Address RangesAGP Aperture Space Device 0 BAR AGP Memory and Prefetchable Memory AGP Dram Graphics Aperture System Management Mode SMM Memory Range Tseg SMM Space DefinitionSMM Space Restrictions SMM Space Address Ranges Hub Interface Decode Rules I/O Address SpaceIntel MCH Decode Rules and Cross-Bridge Address Mapping AGP Interface Decode Rules Cycles Initiated Using AGP FRAME# Protocol DBI30# System BusDynamic Bus Inversion Upstream Interrupt Messages System Bus Interrupt Delivery Single Data Rate SDR Sdram Interface Overview Memory Organization and ConfigurationSupported Dimm Configurations System Memory Interface Byte Function Data Bytes on Dimm Used for Programming Dram Registers Address Translation and Decoding Memory Address Translation and Decoding AGP Target Operations AGP Interface OverviewDram Performance Description Response as PCIx Target BE30# MCH Host Bridge Command Encoding Fast Writes AGP Signal LevelsAGP Transaction Ordering 4 4x AGP Protocol Data Rate Control Bits PCI Command BE30# Intel MCH EncodingAGP FRAME# Transactions on AGP 116 Processor Power State Control Power and Thermal Management Sleep State Control Intel MCH System Reset and Power SequencingIntel MCH Clocking Absolute Maximum Ratings Power CharacteristicsPower Characteristics Absolute Maximum Ratings Signal Signal Type Signals Signal GroupsSignal Groups BCLK, BCLK# DC Characteristics DC Characteristics Intel 82845 MCH for SDR Datasheet 123 124 Ballout and Package Information Intel 82845 MCH Ballout Diagram Top View-Left Side Intel 82845 MCH Ballout Diagram Top View-Right Side Signal Name Ball # AA5 HADSTB0# HADSTB1#AA2 AB5 130 SBA7 SBA4SBA5 SBA6 132 VSSA0 VSSA1 Package Mechanical Information Intel MCH FC-BGA Package Dimensions Top and Side View Intel MCH FC-BGA Package Dimensions Bottom View 136 XOR Tree Chain XOR Test Mode Initialization AE6 HDSTBP1# Chain 0 Ball Element # Signal Name Initial LogicXOR Chains XOR Chain SCK10 Chain 1 Ball Element # Signal Name Initial Logic SDQ65 Chain 2 Ball Element # Signal Name Initial Logic LevelSDQ22 SDQ64 Chain 3 Ball Element # Signal Name Initial Logic LevelSBCS1 Adstb Chain 4 Ball Element # Signal Name Initial Logic Level Gado Chain 5 Ball Element # Signal Name Initial Logic Level Intel 82845 MCH for SDR Datasheet 145 AH9 DBI2# Chain 6 Ball Element # Signal Name Initial Logic Level AD4 HDSTBN0# Chain 7 Ball Element # SDR Ball name Initial Logic LevelAE6 HDSTBN1# AD5 DBI0# 148