Functional Description
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110 Intel® 82845 MCH for SDR Datasheet
Detection of the type of SDRAM installed on the DIMM is supported via a Serial Presence Detect
mechanism as defined in the JEDEC 168-pin DIMM specification. This uses the SCL, SDA and
SA[2:0] pins on the DIMMs to detect the type and size of the installed DIMMs. No special
programmable modes are provided on the MCH for detecting the size and type of memory
installed. Type and size detection must be done via the serial presence detection pins.
Memory Detection and Initialization
Before any cycles to the memory interface can be supported, the MCH SDRAM registers must be
initialized. The MCH must be configured for operation with the installed memory types. Detection
of memory type and size is accomplished via the System Management Bus (SMBus) interface on
the ICH2. This two-wire bus is used to extract the SDRAM type and size information from the
Serial Presence Detect port on the SDRAM DIMMs. SDRAM DIMMs contain a 5-pin Serial
Presence Detect interface, including SCL (serial clock), SDA (serial data), and SA[2:0]. Devices
on the SMBus bus have a seven-bit address. For the SDRAM DIMMs, the upper four bits are
fixed at 1010. The lower three bits are strapped on the SA[2:0] pins. SCL and SDA are connected
directly to the system management bus on the ICH2. Thus, data is read from the Serial Presence
Detect port on the DIMMs via a series of I/O cycles to the ICH2. BIOS needs to determine the
size and type of memory used for each of the rows of memory to properly configure the MCH
memory interface.
SMBus Configuration and Access of the Serial Presence Detect Ports
For more details on SMBus Configuration and Serial Present Detect Ports, see the Intel® 82801BA
I/O Controller Hub 2 (ICH2) and 82801BAM I/O Controller Hub 2 Mobile (ICH2-M) Datasheet.
Memory Register Programming
This section provides an overview of how the required information for programming the SDRAM
registers is obtained from the Serial Presence Detect ports on the DIMMs. The Serial Presence
Detect ports are used to determine refresh rate, MA and MD buffer strength, row type (on a row by
row basis), SDRAM Timings, row sizes and row page sizes. Table 13 lists a subset of the data
available through the on-board Serial Presence Detect ROM on each DIMM.
Table 13. Data Bytes on DIMM Used for Programming DRAM Registers
Byte Function
2 Memory type (SDR SDRAM or DDR SDRAM)
3 Number of row addresses, not count ing bank addresses
4 Number of column addres s es
5 Number of banks of SDRA M (s i ngl e- or doubl e-s ided DIMM)
11 ECC, no ECC
12 Refresh rate
17 Number banks on each device
Table 13 is only a subset of the defined SPD bytes on the DIMMs. These bytes collectively
provide enough data for programming the MCH SDRAM regist e rs.