
Functional Description
R
5.2.2.1Configuration Mechanism For DIMMs
Detection of the type of SDRAM installed on the DIMM is supported via a Serial Presence Detect mechanism as defined in the JEDEC
Memory Detection and Initialization
Before any cycles to the memory interface can be supported, the MCH SDRAM registers must be initialized. The MCH must be configured for operation with the installed memory types. Detection of memory type and size is accomplished via the System Management Bus (SMBus) interface on the ICH2. This
SMBus Configuration and Access of the Serial Presence Detect Ports
For more details on SMBus Configuration and Serial Present Detect Ports, see the Intel® 82801BA I/O Controller Hub 2 (ICH2) and 82801BAM I/O Controller Hub 2 Mobile
Memory Register Programming
This section provides an overview of how the required information for programming the SDRAM registers is obtained from the Serial Presence Detect ports on the DIMMs. The Serial Presence Detect ports are used to determine refresh rate, MA and MD buffer strength, row type (on a row by row basis), SDRAM Timings, row sizes and row page sizes. Table 13 lists a subset of the data available through the
Table 13. Data Bytes on DIMM Used for Programming DRAM Registers
Byte | Function |
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|
2 | Memory type (SDR SDRAM or DDR SDRAM) |
|
|
3 | Number of row addresses, not counting bank addresses |
4 | Number of column addresses |
|
|
5 | Number of banks of SDRAM (single- or |
11 | ECC, no ECC |
|
|
12 | Refresh rate |
17 | Number banks on each device |
|
|
| Table 13 is only a subset of the defined SPD bytes on the DIMMs. These bytes collectively |
| provide enough data for programming the MCH SDRAM registers. |
110 | Intel® 82845 MCH for SDR Datasheet |