Intel 845 manual MBASE1-Memory Base Address Register Device, MEMORYBASE1 ≤ address ≤ MEMORYLIMIT1

Register Description

R

3.6.17MBASE1—Memory Base Address Register (Device 1)

Address Offset:	20–21h
Default Value:	FFF0h
Access:	R/W
Size:	16 bits

This register controls the host to AGP non-prefetchable memory accesses routing based on the following formula:

MEMORY_BASE1 ≤ address ≤ MEMORY_LIMIT1

The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return 0s when read. The configuration software must initialize this register. For the purpose of address decode, address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory address range will be aligned to a 1 MB boundary.

Bit	Description
15:4	Memory Address Base 1 (MEM_BASE1). Corresponds to A[31:20] of the memory address.
3:0	Reserved.

3.6.18MLIMIT1—Memory Limit Address Register (Device 1)

Address Offset:	22–23h
Default Value:	0000h
Access:	R/W
Size:	16 bits

This register controls the host to AGP non-prefetchable memory accesses routing based on the following formula:

MEMORY_BASE1 ≤ address ≤ MEMORY_LIMIT1

The upper 12 bits of the register are read/write and correspond to the upper 12 address bits A[31:20] of the 32-bit address. The bottom 4 bits of this register are read-only and return 0s when read. The configuration software must initialize this register. For the purpose of address decode, address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory address range will be at the top of a 1 MB aligned memory block.

Bit	Description
15:4	Memory Address Limit 1(MEM_LIMIT1). Corresponds to A[31:20] of the memory address.
	Default=0
3:0	Reserved.

Note: Memory range covered by MBASE1 and MLIMIT1 registers are used to map non-prefetchable AGP address ranges (typically, where control/status memory-mapped I/O data structures of the graphics controller will reside) and PMBASE 1and PMLIMIT1 Registers are used to map prefetchable address ranges (typically, graphics local memory). This segregation allows application of USWC space attributes to be performed in a true plug-and-play manner to the prefetchable address range for improved host-AGP memory access performance.

90 Intel® 82845 MCH for SDR Datasheet