Electrical Characteristics
R
6.3Signal Groups
The signal description includes the type of buffer used for the particular signal:
AGTL+ | Open Drain AGTL+ interface signal. Refer to the AGTL+ I/O Specification for |
| complete details. The MCH integrates most AGTL+ termination resistors. |
AGP | AGP interface signals. These signals are compatible with AGP 2.0 1.5 V |
| Signaling Environment DC and AC Specifications. The buffers are not 3.3 V |
| tolerant. |
HI CMOS | Hub Interface 1.8 V CMOS buffers. |
SM CMOS | System memory 3.3 V CMOS buffers. |
Table 20. Signal Groups
Signal | Signal Type | Signals |
Group |
|
|
|
|
|
(a) | AGTL+ I/O | ADS#, BNR#, BR0#,DBSY#, DBI[3:0]#, DRDY#, HA[31:3]#, |
|
| HADSTB[1:0] #, HD[63:0]#, HDSTBP[3:0]#, HDSTBN[3:0]#, HIT#, |
|
| HITM#, HREQ[4:0]# |
|
|
|
(b) | AGTL+ Output | BPRI#, CPURST#, DEFER#, HTRDY#, RS[2:0]# |
|
|
|
(c) | AGTL+ Input | HLOCK# |
|
|
|
(d) | Host Reference | HVREF, HSWING[1:0] |
| Voltages |
|
|
|
|
(e) | AGP I/O | AD_STB0, AD_STB0#, AD_STB1, AD_STB1#, G_FRAME#, |
|
| G_IRDY#, G_TRDY#, G_STOP#, G_DEVSEL#, G_AD[31:0], |
|
| G_C/BE[3:0]#, G_PAR |
|
|
|
(f) | AGP Input | PIPE#, SBA[7:0], RBF#, WBF#, SB_STB, SB_STB#, G_REQ# |
|
|
|
(g) | AGP Output | ST[2:0], G_GNT# |
|
|
|
(h) | AGP Reference | AGPREF |
| Voltage |
|
|
|
|
(i) | Hub Interface’s | HI_[10:0], HI_STB, HI_STB# |
| CMOS I/O |
|
|
|
|
(j) | Hub Interface | HI_REF |
| Reference Voltage |
|
|
|
|
(k) | SDRAM CMOS I/O | SDQ[63:0], SCB[7:0] |
|
|
|
(l) | SDRAM CMOS | SCS[11:0]#, SMA[12:0], SBS[1:0], SRAS#, SCAS#, SWE#, |
| Output | SCKE[5:0], SCK[11:0], RDCLKO |
|
|
|
(m) | SDRAM CMOS Input | RDCLKI |
|
|
|
(n) | SDRAM Reference | SDREF |
| Voltage |
|
|
|
|
(o) | CMOS Input | TESTIN# |
|
|
|
(p) | CMOS Input | RSTIN# (3.3V) |
|
|
|
(r) | AGTL+ Termination | VTT |
| Voltage |
|
|
|
|
120 | Intel® 82845 MCH for SDR Datasheet |
