
Testability
R
Chain 7 Ball | Element # | SDR Ball name | Note | Initial Logic Level |
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AC3 | 25 | HD13# | Input | 1 |
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AB5 | 26 | HD1# | Input | 1 |
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AC5 | 27 | HD5# | Input | 1 |
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AA6 | 28 | HD7# | Input | 1 |
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AA5 | 29 | HD2# | Input | 1 |
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AB3 | 30 | HD3# | Input | 1 |
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AA3 | 31 | HD6# | Input | 1 |
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AB4 | 32 | HD4# | Input | 1 |
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AA2 | 33 | HD0# | Input | 1 |
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Y5 | 34 | HIT# | Input | 1 |
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Y7 | 35 | BPRI# | Input | 1 |
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W6 | 36 | RS2# | Input | 1 |
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Y3 | 37 | HITM# | Input | 1 |
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U7 | 38 | HTRDY# | Input | 1 |
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W5 | 39 | HLOCK# | Input | 1 |
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V7 | 40 | BR0# | Input | 1 |
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W3 | 41 | BNR# | Input | 1 |
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W2 | 41 | RS0# | Input | 1 |
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V5 | 43 | DBSY# | Input | 1 |
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V4 | 44 | DRDY# | Input | 1 |
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AE25 | 45 | SBA7 | Output | N/A |
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148 | Intel® 82845 MCH for SDR Datasheet |