Texas Instruments TMS320C645x manuals
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Texas Instruments TMS320C645x Manual
27 pages 118.69 Kb
218 pages 3.13 Mb
3 Contents13 Read This FirstAbout This Manual Notational Conventions Related Documentation From Texas Instruments 1 Overview 1.1 General RapidIO System User's Guide 14 Serial RapidIO (SRIO)Overview 15 Figure 1. RapidIO Architectural Hierarchy16 Serial RapidIO (SRIO) SPRU976 March 2006Submit Documentation Feedback (1) InfiniBand is a trademark of the InfiniBand Trade Association. 17 1.2 RapidIO Feature Support in SRIO18 1.3 Standards1.4 External Devices Requirements 19 2 SRIO Functional Description 2.1 Overview24 2.2 SRIO Pins2.3 Functional Operation 73 3 Logical/Transport Error Handling and Logging74 4 Interrupt Conditions 4.1 CPU Interrupts4.2 General Description 75 4.3 Interrupt Condition Control Registers83 4.4 Interrupt Status Decode Registers85 4.5 Interrupt Generation4.6 Interrupt Pacing 86 4.7 Interrupt Handling88 5 SRIO Registers 5.1 Introduction99 5.2 Peripheral Identification Register (PID)Table 29. Peripheral ID Register (PID) Field Descriptions 100 5.3 Peripheral Control Register (PCR)Table 30. Peripheral Control Register (PCR) Field Descriptions 101 5.4 Peripheral Settings Control Register (PER_SET_CNTL)104 5.5 Peripheral Global Enable Register (GBL_EN)Figure 61. Peripheral Global Enable Register (GBL_EN) Table 32. Peripheral Global Enable Register (GBL_EN) Field Descriptions 105 5.6 Peripheral Global Enable Status Register (GBL_EN_STAT)Figure 62. Peripheral Global Enable Status Register (GBL_EN_STAT) Table 33. Peripheral Global Enable Status Register (GBL_EN_STAT) Field Descriptions 106 5.7 Block n Enable Register (BLK n_EN)Table 34. Block nEnable Register (BLK n_EN) Field Descriptions 107 5.8 Block n Enable Status Register (BLK n_EN_STAT)Table 35. Block nEnable Status Register (BLK n_EN_STAT) Field Descriptions 108 5.9 RapidIO DEVICEID1 Register (DEVICEID_REG1)Figure 65. RapidIO DEVICEID1 Register (DEVICEID_REG1) Table 36. RapidIO DEVICEID1 Register (DEVICEID_REG1) Field Descriptions 109 5.10 RapidIO DEVICEID2 Register (DEVICEID_REG2)Figure 66. RapidIO DEVICEID2 Register (DEVICEID_REG2) Table 37. RapidIO DEVICEID2 Register (DEVICEID_REG2) Field Descriptions 110 5.11 Packet Forwarding Register n for 16b DeviceIDs (PF_16B_CNTL n)111 5.12 Packet Forwarding Register n for 8b DeviceIDs (PF_8B_CNTL n)Figure 68. Packet Forwarding Register nfor 8b DeviceIDs (PF_8B_CNTL n) Table 39. Packet Forwarding Register nfor 8b DeviceIDs (PF_8B_CNTL n) Field Descriptions 112 5.13 SERDES Receive Channel Configuration Registers n (SERDES_CFGRX n_CNTL)Table 40. SERDES Receive Channel Configuration Registers n(SERDES_CFGRX n_CNTL) FieldDescriptions 113 Table 41. EQ Bits114 5.14 SERDES Transmit Channel Configuration Registers n (SERDES_CFGTX n_CNTL)Figure 70. SERDES Transmit Channel Configuration Registers n(SERDES_CFGTX n_CNTL) Table 42. SERDES Transmit Channel Configuration Registers n(SERDES_CFGTX n_CNTL) FieldDescriptions 115 Table 43. SWING BitsTable 44. DE Bits 116 5.15 SERDES Macro Configuration Register n (SERDES_CFG n_CNTL)Figure 71. SERDES Macros CFG (0-3) Registers (SERDES_CFG n_CNTL) Table 45. SERDES Macros CFG (0-3) Registers (SERDES_CFG n_CNTL) Field Descriptions 117 5.16 DOORBELL n Interrupt Status Register (DOORBELL n_ICSR)118 5.17 DOORBELL n Interrupt Clear Register (DOORBELL n_ICCR)119 5.18 RX CPPI Interrupt Status Register (RX_CPPI_ICSR)Figure 74. RX CPPI Interrupt Status Register (RX_CPPI_ICSR) Table 48. RX CPPI Interrupt Status Register (RX_CPPI_ICSR) Field Descriptions 120 5.19 RX CPPI Interrupt Clear Register (RX_CPPI_ICCR)Figure 75. RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) Table 49. RX CPPI Interrupt Clear Register (RX_CPPI_ICCR) Field Descriptions 121 5.20 TX CPPI Interrupt Status Register (TX_CPPI_ICSR)Figure 76. TX CPPI Interrupt Status Register (TX_CPPI_ICSR) Table 50. TX CPPI Interrupt Status Register (TX_CPPI_ICSR) Field Descriptions 122 5.21 TX CPPI Interrupt Clear Register (TX_CPPI_ICCR)Figure 77. TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) Table 51. TX CPPI Interrupt Clear Register (TX_CPPI_ICCR) Field Descriptions 123 5.22 LSU Status Interrupt Register (LSU_ICSR)Figure 78. LSU Status Interrupt Register (LSU_ICSR) Table 52. LSU Status Interrupt Register (LSU_ICSR) Field Descriptions 124 5.23 LSU Clear Interrupt Register (LSU _ICCR)Figure 79. LSU Clear Interrupt Register (LSU _ICCR) Table 53. LSU Clear Interrupt Register (LSU _ICCR) Field Descriptions 125 5.24 Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR)Figure 80. Error, Reset, and Special Event Status Interrupt Register (ERR_RST_EVNT_ICSR) 126 5.25 Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR)Figure 81. Error, Reset, and Special Event Clear Interrupt Register (ERR_RST_EVNT_ICCR) 127 5.26 DOORBELL n Interrupt Condition Routing Register (DOORBELL n_ICRR)128 5.27 DOORBELL n Interrupt Condition Routing Register 2 (DOORBELL n_ICRR2)129 5.28 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR)Figure 84. RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) Table 58. RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR) Field Descriptions 130 5.29 RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2)Figure 85. RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) Table 59. RX CPPI Interrupt Condition Routing Register (RX_CPPI _ICRR2) Field Descriptions 131 5.30 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR)Figure 86. TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) Table 60. TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR) Field Descriptions 132 5.31 TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2)Figure 87. TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) Table 61. TX CPPI Interrupt Condition Routing Register (TX_CPPI _ICRR2) Field Descriptions 133 5.32 LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0)Figure 88. LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) Table 62. LSU Module Interrupt Condition Routing Register 0 (LSU_ICRR0) Field Descriptions 134 5.33 LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1)Figure 89. LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) Table 63. LSU Module Interrupt Condition Routing Register 1 (LSU_ICRR1) Field Descriptions 135 5.34 LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2)Figure 90. LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) Table 64. LSU Module Interrupt Condition Routing Register 2 (LSU_ICRR2) Field Descriptions 136 5.35 LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3)Figure 91. LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) Table 65. LSU Module Interrupt Condition Routing Register 3 (LSU_ICRR3) Field Descriptions 137 5.36 Error, Reset, and Special Event Interrupt Condition Routing Register(ERR_RST_EVNT_ICRR)Figure 92. Error, Reset, and Special Event Interrupt Condition Routing Register(ERR_RST_EVNT_ICRR) 138 5.37 Error, Reset, and Special Event Interrupt Condition Routing Register 2(ERR_RST_EVNT_ICRR2) 139 5.38 Error, Reset, and Special Event Interrupt Condition Routing Register 3(ERR_RST_EVNT_ICRR3) 140 5.39 INTDST n Interrupt Status Decode Registers (INTDST n_DECODE)141 5.40 INTDST n Interrupt Rate Control Registers (INTDST n_RATE_CNTL)142 5.41 LSU n Control Register 0 (LSU n_REG0)143 5.42 LSU n Control Register 1 (LSU n_REG1)Figure 98. LSU nControl Register 1 (LSU n_REG1) Table 72. LSU nControl Register 1 (LSU n_REG1) Field Descriptions 144 5.43 LSU n Control Register 2 (LSU n_REG2)145 5.44 LSU n Control Register 3 (LSU n_REG3)146 5.45 LSU n Control Register 4 (LSU n_REG4)Figure 101. LSU nControl Register 4 (LSU n_REG4) Table 75. LSU nControl Register 4 (LSU n_REG4) Field Descriptions 147 5.46 LSU n Control Register 5 (LSU n_REG5)148 5.47 LSU n Control Register 6 (LSU n_REG6)Figure 103. LSU nControl Register 6 (LSU n_REG6) Table 77. LSU nControl Register 6 (LSU n_REG6) Field Descriptions 149 5.48 LSU Congestion Control Flow Mask n (LSU_FLOW_MASKS n)Figure 104. LSU Congestion Control Flow Mask n(LSU_FLOW_MASKS n) Table 78. LSU Congestion Control Flow Mask n(LSU_FLOW_MASKS n) Field Descriptions 150 5.49 Queue Transmit DMA Head Descriptor Pointer Registers (QUEUE n_TXDMA_HDP)151 5.50 Queue Transmit DMA Completion Pointer Registers (QUEUE n_TXDMA_CP)152 5.51 Queue Receive DMA Head Descriptor Pointer Registers (QUEUE n_RXDMA_HDP)153 5.52 Queue Receive DMA Completion Pointer Registers (QUEUE n_RXDMA_CP)154 5.53 Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN)Figure 109. Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Table 83. Transmit Queue Teardown Register (TX_QUEUE_TEAR_DOWN) Field Descriptions 155 5.54 Transmit CPPI Supported Flow Mask Registers n (TX_CPPI_FLOW_MASKS n)157 5.55 Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN)Figure 111. Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) Table 85. Receive Queue Teardown Register (RX_QUEUE_TEAR_DOWN) Field Descriptions 158 5.56 Receive CPPI Control Register (RX_CPPI_CNTL)Figure 112. Receive CPPI Control Register (RX_CPPI_CNTL) Table 86. Receive CPPI Control Register (RX_CPPI_CNTL) Field Descriptions 159 5.57 Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0)Figure 113. Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0) Table 87. Transmit CPPI Weighted Round Robin Control Register 0 (TX_QUEUE_CNTL0) FieldDescriptions 160 5.58 Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1)Figure 114. Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1) Table 88. Transmit CPPI Weighted Round Robin Control Register 1 (TX_QUEUE_CNTL1) FieldDescriptions 161 5.59 Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2)Figure 115. Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2) Table 89. Transmit CPPI Weighted Round Robin Control Register 2 (TX_QUEUE_CNTL2) FieldDescriptions 162 5.60 Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3)Figure 116. Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3) Table 90. Transmit CPPI Weighted Round Robin Control Register 3 (TX_QUEUE_CNTL3) FieldDescriptions 163 5.61 Mailbox-to-Queue Mapping Register L n (RXU_MAP_L n)Figure 117. Mailbox-to-Queue Mapping Register L n(RXU_MAP_L n) Table 91. Mailbox-to-Queue Mapping Register L n(RXU_MAP_L n) Field Descriptions 164 5.62 Mailbox-to-Queue Mapping Register H n (RXU_MAP_H n)Figure 118. Mailbox-to-Queue Mapping Register H n(RXU_MAP_H n) Table 92. Mailbox-to-Queue Mapping Register H n(RXU_MAP_H n) Field Descriptions 165 5.63 Flow Control Table Entry Registers (FLOW_CNTL n)There are sixteen of these registers. Figure 119. Flow Control Table Entry Registers (FLOW_CNTL n) Table 93. Flow Control Table Entry Registers (FLOW_CNTL n) Field Descriptions 166 5.64 Device Identity CAR (DEV_ID)Figure 120. Device Identity CAR (DEV_ID) Table 94. Device Identity CAR (DEV_ID) Field Descriptions 167 5.65 Device Information CAR (DEV_INFO)Figure 121. Device Information CAR (DEV_INFO) Table 95. Device Information CAR (DEV_INFO) Field Descriptions 168 5.66 Assembly Identity CAR (ASBLY_ID)Figure 122. Assembly Identity CAR (ASBLY_ID) Table 96. Assembly Identity CAR (ASBLY_ID) Field Descriptions 169 5.67 Assembly Information CAR (ASBLY_INFO)Figure 123. Assembly Information CAR (ASBLY_INFO) Table 97. Assembly Information CAR (ASBLY_INFO) Field Descriptions 170 5.68 Processing Element Features CAR (PE_FEAT)Figure 124. Processing Element Features CAR (PE_FEAT) Table 98. Processing Element Features CAR (PE_FEAT) Field Descriptions 171 5.69 Source Operations CAR (SRC_OP)Figure 125. Source Operations CAR (SRC_OP) Table 99. Source Operations CAR (SRC_OP) Field Descriptions 172 5.70 Destination Operations CAR (DEST_OP)Figure 126. Destination Operations CAR (DEST_OP) Table 100. Destination Operations CAR (DEST_OP) Field Descriptions 173 5.71 Processing Element Logical Layer Control CSR (PE_LL_CTL)Figure 127. Processing Element Logical Layer Control CSR (PE_LL_CTL) Table 101. Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions 174 5.72 Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR)Figure 128. Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) Table 102. Local Configuration Space Base Address 0 CSR (LCL_CFG_HBAR) Field Descriptions 175 5.73 Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR)Figure 129. Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) Table 103. Local Configuration Space Base Address 1 CSR (LCL_CFG_BAR) Field Descriptions 176 5.74 Base Device ID CSR (BASE_ID)Figure 130. Base Device ID CSR (BASE_ID) Table 104. Base Device ID CSR (BASE_ID) Field Descriptions 177 5.75 Host Base Device ID Lock CSR (HOST_BASE_ID_LOCK)178 5.76 Component Tag CSR (COMP_TAG)Figure 132. Component Tag CSR (COMP_TAG) Table 106. Component Tag CSR (COMP_TAG) Field Descriptions 179 5.77 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD)Figure 133. 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) Table 107. 1x/4x LP_Serial Port Maintenance Block Header Register (SP_MB_HEAD) FieldDescriptions 180 5.78 Port Link Time-Out Control CSR (SP_LT_CTL)Figure 134. Port Link Time-Out Control CSR (SP_LT_CTL) Table 108. Port Link Timeout Control CSR (SP_LT_CTL) Field Descriptions 181 5.79 Port Response Time-Out Control CSR (SP_RT_CTL)Figure 135. Port Response Time-Out Control CSR (SP_RT_CTL) Table 109. Port Response Time-Out Control CSR (SP_RT_CTL) Field Descriptions 182 5.80 Port General Control CSR (SP_GEN_CTL)Figure 136. Port General Control CSR (SP_GEN_CTL) Table 110. Port General Control CSR (SP_GEN_CTL) Field Descriptions 183 5.81 Port Link Maintenance Request CSR n (SP n_LM_REQ)184 5.82 Port Link Maintenance Response CSR n (SP n_LM_RESP)Figure 138. Port Link Maintenance Response CSR n(SP n_LM_RESP) Table 112. Port Link Maintenance Response CSR n(SP n_LM_RESP) Field Descriptions 185 5.83 Port Local AckID Status CSR n (SP n_ACKID_STAT)Figure 139. Port Local AckID Status CSR n(SP n_ACKID_STAT) Table 113. Port Local AckID Status CSR n(SP n_ACKID_STAT) Field Descriptions 186 5.84 Port Error and Status CSR n (SP n_ERR_STAT)Figure 140. Port Error and Status CSR n(SP n_ERR_STAT) Table 114. Port Error and Status CSR n(SP n_ERR_STAT) Field Descriptions 188 5.85 Port Control CSR n (SP n_CTL)190 5.86 Error Reporting Block Header (ERR_RPT_BH)Figure 142. Error Reporting Block Header (ERR_RPT_BH) Table 116. Error Reporting Block Header (ERR_RPT_BH) Field Descriptions 191 5.87 Logical/Transport Layer Error Detect CSR (ERR_DET)Figure 143. Logical/Transport Layer Error Detect CSR (ERR_DET) Table 117. Logical/Transport Layer Error Detect CSR (ERR_DET) Field Descriptions 192 5.88 Logical/Transport Layer Error Enable CSR (ERR_EN)Figure 144. Logical/Transport Layer Error Enable CSR (ERR_EN) Table 118. Logical/Transport Layer Error Enable CSR (ERR_EN) Field Descriptions 193 5.89 Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT)Figure 145. Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) Table 119. Logical/Transport Layer High Address Capture CSR (H_ADDR_CAPT) Field Descriptions 194 5.90 Logical/Transport Layer Address Capture CSR (ADDR_CAPT)Figure 146. Logical/Transport Layer Address Capture CSR (ADDR_CAPT) Table 120. Logical/Transport Layer Address Capture CSR (ADDR_CAPT) Field Descriptions 195 5.91 Logical/Transport Layer Device ID Capture CSR (ID_CAPT)Figure 147. Logical/Transport Layer Device ID Capture CSR (ID_CAPT) Table 121. Logical/Transport Layer Device ID Capture CSR (ID_CAPT) Field Descriptions 196 5.92 Logical/Transport Layer Control Capture CSR (CTRL_CAPT)Figure 148. Logical/Transport Layer Control Capture CSR (CTRL_CAPT) Table 122. Logical/Transport Layer Control Capture CSR (CTRL_CAPT) Field Descriptions 197 5.93 Port-Write Target Device ID CSR (PW_TGT_ID)Figure 149. Port-Write Target Device ID CSR (PW_TGT_ID) Table 123. Port-Write Target Device ID CSR (PW_TGT_ID) Field Descriptions 198 5.94 Port Error Detect CSR n (SP n_ERR_DET)Figure 150. Port Error Detect CSR n(SP n_ERR_DET) Table 124. Port Error Detect CSR n(SP n_ERR_DET) Field Descriptions 199 5.95 Port Error Rate Enable CSR n (SP n_RATE_EN)Figure 151. Port Error Rate Enable CSR n(SP n_RATE_EN) Table 125. Port Error Rate Enable CSR n(SP n_RATE_EN) Field Descriptions 200 5.96 Port n Attributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0)Figure 152. Port nAttributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0) Table 126. Port nAttributes Error Capture CSR 0 (SP n_ERR_ATTR_CAPT_DBG0) FieldDescriptions 201 5.97 Port n Packet/Control Symbol Error Capture CSR 1 (SP n_ERR_CAPT_DBG1)202 5.98 Port n Packet/Control Symbol Error Capture CSR 2 (SP n_ERR_CAPT_DBG2)203 5.99 Port n Packet/Control Symbol Error Capture CSR 3 (SP n_ERR_CAPT_DBG3)204 5.100 Port n Packet/Control Symbol Error Capture CSR 4 (SP n_ERR_CAPT_DBG4)205 5.101 Port Error Rate CSR n (SP n_ERR_RATE)Figure 157. Port Error Rate CSR n(SP n_ERR_RATE) Table 131. Port Error Rate CSR n(SP n_ERR_RATE) Field Descriptions 206 5.102 Port Error Rate Threshold CSR n (SP n_ERR_THRESH)Figure 158. Port Error Rate Threshold CSR n(SP n_ERR_THRESH) Table 132. Port Error Rate Threshold CSR n(SP n_ERR_THRESH) Field Descriptions 207 5.103 Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER)Figure 159. Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) Table 133. Port IP Discovery Timer in 4x mode (SP_IP_DISCOVERY_TIMER) Field Descriptions 208 5.104 Port IP Mode CSR (SP_IP_MODE)210 5.105 Serial Port IP Prescalar (IP_PRESCAL)Figure 161. Serial Port IP Prescalar (IP_PRESCAL) Table 135. Serial Port IP Prescalar (IP_PRESCAL) Field Descriptions 211 5.106 Port-Write-In Capture CSR n (SP_IP_PW_IN_CAPT n)212 5.107 Port Reset Option CSR n (SP n_RST_OPT)213 5.108 Port Control Independent Register n (SP n_CTL_INDEP)215 5.109 Port Silence Timer n (SP n_SILENCE_TIMER)Figure 165. Port Silence Timer n(SP n_SILENCE_TIMER) Table 139. Port Silence Timer n(SP n_SILENCE_TIMER) Field Descriptions 216 5.110 Port Multicast-Event Control Symbol Request Register n (SP n_MULT_EVNT_CS)217 5.111 Port Control Symbol Transmit n (SP n_CS_TX)Figure 167. Port Control Symbol Transmit n(SP n_CS_TX) Table 141. Port Control Symbol Transmit n(SP n_CS_TX) Field Descriptions
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