Texas Instruments TMS320C645x Interrupt Handling, INTDSTnRATECNTL Interrupt Rate Control Register

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Interrupt Conditions

Figure 57. INTDSTn_RATE_CNTL Interrupt Rate Control Register

31 0

32-bit Count Down Value

R/W-0

LEGEND: R = Read, W = Write, n = value at reset

Offsets:

∙INTDST0 – 0x0320

∙INTDST1 – 0x0324

∙INTDST2 – 0x0328

∙INTDST3 – 0x032C

∙INTDST4 – 0x0330

∙INTDST5 – 0x0334

∙INTDST6 – 0x0338

∙INTDST7 – 0x033C

4.7Interrupt Handling

Interrupts are either signaled externally through RapidIO packets, or internally by state machines in the peripheral. CPU servicing interrupts are signaled externally by the DOORBELL RapidIO packet in Direct I/O mode, or internally by the CPPI module (described in section 8) in the message passing mode. Error Status interrupts are signaled when error counting logic within the peripheral have reached their thresholds. In either case, it is the peripheral that signals the interrupt and sets the corresponding status bits.

When the CPU is interrupted, it reads the ICSR registers to determine the source of the interrupt and appropriate action to take. For example, if it is a DOORBELL interrupt, the CPU will read from an L2 address that is specified by its circular buffer read pointer that is managed by software. There may be more than one circular buffer for each core. The correct circular buffer to read from and increment depends on the bit set in the ICSR register. The CPU then clears the status bit.

For Error Status interrupts, the peripheral must indicate to all the CPUs that one of the link ports has reached the error threshold. In this case, the peripheral sets the status bit indicating degraded or failed limits have been reached, and an interrupt is generated to each core through the ICRR mapping. The cores can then scan the ICSR registers to determine the port with the error problems. Further action can then be taken as determined by the application.

Interrupt Handler

temp1 = SRIO_REGS->TX_CPPI_ICSR;

if ((temp1 & 0x00000001) == 0x00000001)

{

SRIO_REGS->Queue0_TxDMA_CP = (int )TX_DESCP0_0;

}

temp2 = SRIO_REGS->RX_CPPI_ICSR;

if ((temp2 & 0x00000001) == 0x00000001)

{

SRIO_REGS->Queue0_RXDMA_CP = (int )RX_DESCP0_0;

}

interruptStatus[0] = SRIO_REGS->DOORBELL3_ICSR; interruptStatus[1] = SRIO_REGS->DOORBELL3_ICCR; interruptStatus[2] = SRIO_REGS->LSU_ICSR; interruptStatus[3] = SRIO_REGS->LSU_ICCR; interruptStatus[4] = SRIO_REGS->DOORBELL3_ICRR; interruptStatus[5] = SRIO_REGS->DOORBELL3_ICRR2; interruptStatus[6] = SRIO_REGS->LSU_ICRR; interruptStatus[7] = SRIO_REGS->LSU_ICRR2; interruptStatus[8] = SRIO_REGS->INTDST0_Decode; interruptStatus[9] = SRIO_REGS->ERR_RST_EVNT_ICRR; interruptStatus[10] = SRIO_REGS->INTDST0_Rate_CNTL;

86 Serial RapidIO (SRIO) SPRU976 –March 2006

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