Texas Instruments TMS320C645x RXUMAPL18, RXUMAPH18, RXUMAPL19, RXUMAPH19, RXUMAPL20, RXUMAPH20

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			SRIO Registers
	Table 28. Serial Rapid IO (SRIO) Registers		(continued)
Offset	Acronym	Register Description	Section
0x0890	RXU_MAP_L18	MailBox-to-Queue Mapping Register L18	Section 5.61
0x0894	RXU_MAP_H18	MailBox-to-Queue Mapping Register H18	Section 5.62
0x0898	RXU_MAP_L19	MailBox-to-Queue Mapping Register L19	Section 5.61
0x089C	RXU_MAP_H19	MailBox-to-Queue Mapping Register H19	Section 5.62
0x08A0	RXU_MAP_L20	MailBox-to-Queue Mapping Register L20	Section 5.61
0x08A4	RXU_MAP_H20	MailBox-to-Queue Mapping Register H20	Section 5.62
0x08A8	RXU_MAP_L21	MailBox-to-Queue Mapping Register L21	Section 5.61
0x08AC	RXU_MAP_H21	MailBox-to-Queue Mapping Register H21	Section 5.62
0x08B0	RXU_MAP_L22	MailBox-to-Queue Mapping Register L22	Section 5.61
0x08B4	RXU_MAP_H22	MailBox-to-Queue Mapping Register H22	Section 5.62
0x08B8	RXU_MAP_L23	MailBox-to-Queue Mapping Register L23	Section 5.61
0x08BC	RXU_MAP_H23	MailBox-to-Queue Mapping Register H23	Section 5.62
0x08C0	RXU_MAP_L24	MailBox-to-Queue Mapping Register L24	Section 5.61
0x08C4	RXU_MAP_H24	MailBox-to-Queue Mapping Register H24	Section 5.62
0x08C8	RXU_MAP_L25	MailBox-to-Queue Mapping Register L25	Section 5.61
0x08CC	RXU_MAP_H25	MailBox-to-Queue Mapping Register H25	Section 5.62
0x08D0	RXU_MAP_L26	MailBox-to-Queue Mapping Register L26	Section 5.61
0x08D4	RXU_MAP_H26	MailBox-to-Queue Mapping Register H26	Section 5.62
0x08D8	RXU_MAP_L27	MailBox-to-Queue Mapping Register L27	Section 5.61
0x08DC	RXU_MAP_H27	MailBox-to-Queue Mapping Register H27	Section 5.62
0x08E0	RXU_MAP_L28	MailBox-to-Queue Mapping Register L28	Section 5.61
0x08E4	RXU_MAP_H28	MailBox-to-Queue Mapping Register H28	Section 5.62
0x08E8	RXU_MAP_L29	MailBox-to-Queue Mapping Register L29	Section 5.61
0x08EC	RXU_MAP_H29	MailBox-to-Queue Mapping Register H29	Section 5.62
0x08F0	RXU_MAP_L30	MailBox-to-Queue Mapping Register L30	Section 5.61
0x08F4	RXU_MAP_H30	MailBox-to-Queue Mapping Register H30	Section 5.62
0x08F8	RXU_MAP_L31	MailBox-to-Queue Mapping Register L31	Section 5.61
0x08FC	RXU_MAP_H31	MailBox-to-Queue Mapping Register H31	Section 5.62
0x0900	FLOW_CNTL0	Flow Control Table Entry Register 0	Section 5.63
0x0904	FLOW_CNTL1	Flow Control Table Entry Register 1	Section 5.63
0x0908	FLOW_CNTL2	Flow Control Table Entry Register 2	Section 5.63
0x090C	FLOW_CNTL3	Flow Control Table Entry Register 3	Section 5.63
0x0910	FLOW_CNTL4	Flow Control Table Entry Register 4	Section 5.63
0x0914	FLOW_CNTL5	Flow Control Table Entry Register 5	Section 5.63
0x0918	FLOW_CNTL6	Flow Control Table Entry Register 6	Section 5.63
0x091C	FLOW_CNTL7	Flow Control Table Entry Register 7	Section 5.63
0x0920	FLOW_CNTL8	Flow Control Table Entry Register 8	Section 5.63
0x0924	FLOW_CNTL9	Flow Control Table Entry Register 9	Section 5.63
0x0928	FLOW_CNTL10	Flow Control Table Entry Register 10	Section 5.63
0x092C	FLOW_CNTL11	Flow Control Table Entry Register 11	Section 5.63
0x0930	FLOW_CNTL12	Flow Control Table Entry Register 12	Section 5.63
0x0934	FLOW_CNTL13	Flow Control Table Entry Register 13	Section 5.63
0x0938	FLOW_CNTL14	Flow Control Table Entry Register 14	Section 5.63
0x093C	FLOW_CNTL15	Flow Control Table Entry Register 15	Section 5.63
0x1000	DEV_ID	Device Identity CAR	Section 5.64
0x1004	DEV_INFO	Device Information CAR	Section 5.65
SPRU976 –March 2006			Serial RapidIO (SRIO)	95

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