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Texas Instruments TMS320C645x manual Txhdp

Models: TMS320C645x

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SRIO Registers

5.49Queue Transmit DMA Head Descriptor Pointer Registers (QUEUEn_TXDMA_HDP)

There are sixteen of these registers.

Figure 105. Queue Transmit DMA Head Descriptor Pointer Registers (QUEUEn_TXDMA_HDP)

31-16

TX_HDP

RW-0x00

LEGEND: R = Read only; -n= value after reset

15-0

TX_HDP

RW-0x00

LEGEND: R = Read only; -n= value after reset

Table 79. Queue Transmit DMA Head Descriptor Pointer Registers (QUEUEn_TXDMA_HDP) Field

Descriptions

Bit	Field	Value Description
31-0	TX_HDP	This field is the host memory address for the first buffer descriptor in the transmit queue. This field
		is written by the host to initiate queue transmit operations and is zeroed by the port when all
		packets in the queue have been transmitted. An error condition results if the host writes this field
		when the current field value is nonzero. The address must be 32-bit word aligned .

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Serial RapidIO (SRIO)

SPRU976 –March 2006

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Texas Instruments TMS320C645x manual Txhdp

Contents

Users Guide Submit Documentation Feedback Contents Errrstevnticrr Base Device ID CSR Baseid List of Figures Load/Store Module Interrupt Condition Routing Registers 150 Port Error Rate Threshold CSR n SP n Errthresh List of Tables LSUn Control Register 0 LSUnREG0 Field Descriptions Base Device ID CSR Baseid Field Descriptions Read This First General RapidIO System RapidIO Architectural HierarchyOverview RapidIO Interconnect Architecture 3 1x/4x LP-SerialRapidIO Feature Support in Srio Features Supported in SrioExternal Devices Requirements Features Not SupportedStandards RapidIO Documents and LinksOverview Peripheral Data FlowSrio Packets Operation SequenceOperation Sequence Example Packet Streaming WriteControl Symbols 4x RapidIO Packet Data Stream Streaming-Write ClassSrio Packet Ftype/Ttype Packet TypeFtype Ttype Packet Type Functional Operation Srio PinsBlock Diagram Pin DescriptionSrio Conceptual Block Diagram Bits of Serdescfg nCNTL Register 0x120 0x12c Serdes and its ConfigurationsEnabling the PLL Bit Name Value DescriptionBits of Serdescfg nCNTL Register 0x120 0x12c Line Rate versus PLL Output Clock FrequencyRate Bit Effects Frequency Range versus MPY Enabling the ReceiverBits of Serdescfgrx nCNTL Registers Disabled. Loss of signal detection disabled Bits of SERDESCFGRXnCNTL RegistersBit Field Value Description 1514 Bits of Serdescfgtx nCNTL Registers EQ BitsEnabling the Transmitter CFGRX2219 Low Freq GainBits of Serdescfgtx nCNTL Registers Swing BitsDE Bits Serdes Configuration Example DirectIOControl/Command Register Field Mapping RapidIO Packet Header FieldStatus Field Function Control/Command Register RapidIO Packet Header FieldStatus Fields BSYLSU Registers Timing Example Burst Nwriter Detailed Data Path DescriptionTX Operation Write TransactionsRead Transactions Segmentation RX OperationReset and Power Down State Message PassingCppi RX Scheme for RapidIO Queue Mapping Table Address Offset 0x0800 0x08FC Queue Mapping Register Rxumapl n Bit Name DescriptionRX Buffer Descriptor Fields RX Buffer Descriptor Field Descriptions Field DescriptionRX Buffer Descriptor Field Descriptions Field DescriptionRX Cppi Mode Explanation Cppi Boundary Diagram TX Buffer Descriptor Fields TX Buffer Descriptor Field DefinitionsUses this bit to reclaim buffers Ssize TXQUEUECNTL1- Address Offset 0x7E4 Name Bit Access Reset Value DescriptionTXQUEUECNTL0- Address Offset 0x7E0 TXQUEUECNTL2- Address Offset 0x7E8TXQueueMap10 2316 0x0A Detailed Data Path Description Message Passing Software Requirements RX OperationTX Operation Initialization Example Queue MappingRX Buffer Descriptor TX Buffer Descriptor NDPMaintenance Start Message PassingDoorbell Doorbell OperationCongestion Control Detailed DescriptionName Bit Transmit Source Flow Control Masks Configuration Bus Example EndiannessReset DMA ExampleReset Summary Enable and Enable Status RegistersBLK8ENSTA BLK7ENSTA Gblen Enable and Enable Status Bit Field DescriptionsEnstat BLK0ENBLK2EN BLK1ENBLK1ENSTAT BLK2ENSTATBLK8ENSTAT Software Shutdown DetailsEmulation Peren Soft FreeEmulation Control Signals Enabling the Srio PeripheralsPeren 11.2 PLL, Ports, Device ID and Data Rate Initializations Peripheral InitializationsSet Device ID Registers Assert the Peren bit to enable logical layer data flow Read register to check portx1-4 OK bitBootload Data Movement Bootload CapabilityConfiguration Device WakeupMSG REQ ERRCPU Interrupts General DescriptionInterrupt Condition Control Registers Interrupt Source Configuration Options Where ICS0 Doorbell1, bit 0, through ICS15 Doorbell1, bit Interrupt Conditions LSU Interrupt Condition Clear Registers Iccr Address Offset ICC11 ICC10 ICC9 ICC8 ICS11 ICS10 ICS9 ICS8ICS2 ICS1 ICS0 ICC2 ICC1 ICC0Interrupt Condition Routing Options DOORBELL0ICRR2 Address OffsetLSUICRR1 Address Offset 0x02E4 LSUICRR2 Address Offset 0x02E8LSUICRR3 Address Offset 0x02EC ERRRSTEVNTICRR3 Address Offset 0x02F8 Interrupt Status Decode RegistersERRRSTEVNTICRR2 Address Offset 0x02F4 ICR2 ICR1 ICR0Sharing of Isdr Bits Interrupt Generation Interrupt PacingISDR3 ISDR2 ISDR1 ISDR9 ISDR8 ISDR7 ISDR6 ISDR5 ISDR4 ISDR0 Interrupt Handling INTDSTnRATECNTL Interrupt Rate Control RegisterInterrupt Conditions Introduction Serial Rapid IO Srio RegistersOffset Acronym Register Description Serial Rapid IO Srio Registers Offset Acronym Register DescriptionRR2 LSUICRR3Errrstevntic RR3LSU3REG1 QUEUE3TXDMAC QUEUE1TXDMACQUEUE2TXDMAC QUEUE4TXDMACQUEUE12RXDMA SKS7 TxcppiflowmaSKS6 RxqueuetearRXUMAPL19 RXUMAPL18RXUMAPH18 RXUMAPH19Pefeat AsblyidAsblyinfo SrcopSP0ERRCAPTDB SP0ERRATTRCAPTDBG0 SP0ERRRATESP3ERRTHRESH TimerSP3ERRRATE SpipdiscoveryType Peripheral Identification Register PIDPeripheral ID Register PID Field Descriptions Class REVPere Soft Free Peripheral Control Register PCRPeripheral Control Register PCR Field Descriptions Bit FieldPeripheral Settings Control Register Persetcntl Prescalerse Cbatranspr1XMODE LectENPLL3 ENPLL2ENPLL1 Peripheral Global Enable Register Gblen Peripheral Global Enable Register Gblen Field DescriptionsENS Peripheral Global Enable Status Register GblenstatGBL TATBlock n Enable Register BLKnEN Block n Enable Register BLKnEN Field DescriptionsBlock n Enable Status Register BLKnENSTAT Block n Enable Status Register BLKnENSTAT8BNODEID RapidIO DEVICEID1 Register DEVICEIDREG1RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions 16BNODEIDRapidIO DEVICEID2 Register DEVICEIDREG2 RapidIO DEVICEID2 Register DEVICEIDREG2 Field DescriptionsPacket Forwarding Register n for 16b DeviceIDs PF16BCNTLn Packet Forwarding Register n for 8b DeviceIDs PF8BCNTLn CDR LOS Align Term Invpa Rate BuswidthCFGRX2219 Low Freq Gain Zero Freq at e28 min Enft Swing Invpa Rate BuswidthEntx CFGTX119 Amplitude mV dfpp Swing BitsDE Bits CFGTX1512 Amplitude ReductionRIOCLK/RIOCLK Serdes Macro Configuration Register n SERDESCFGnCNTLMPY Enpll MPYDOORBELLn Interrupt Status Register DOORBELLnICSR DOORBELLn Interrupt Status Register DOORBELLnICSRDOORBELLn Interrupt Clear Register DOORBELLnICCR DOORBELLn Interrupt Clear Register DOORBELLnICCRRX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Status Register RxcppiicsrRX Cppi Interrupt Clear Register Rxcppiiccr RX Cppi Interrupt Clear Register RxcppiiccrTX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Status Register TxcppiicsrTX Cppi Interrupt Clear Register Txcppiiccr TX Cppi Interrupt Clear Register TxcppiiccrLSU Status Interrupt Register Lsuicsr LSU Status Interrupt Register Lsuicsr Field DescriptionsICS31-0 Load/Store module interrupt condition status bits LSU Clear Interrupt Register LSU Iccr LSU Clear Interrupt Register LSU Iccr Field DescriptionsICS31-0 Load/Store module interrupt clear bits 31-17 126 DOORBELLn Interrupt Condition Routing Register DOORBELLnICRR 128 RX Cppi Interrupt Condition Routing Register Rxcppi Icrr ICR RX Cppi Interrupt condition routing bitsRX Cppi Interrupt Condition Routing Register Rxcppi ICRR2 RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2TX Cppi Interrupt Condition Routing Register Txcppi Icrr ICR TX Cppi Interrupt condition routing bitsTX Cppi Interrupt Condition Routing Register Txcppi ICRR2 TX Cppi Interrupt Condition Routing Register Txcppi ICRR2LSU Module Interrupt Condition Routing Register 0 LSUICRR0 ICRLSU Module Interrupt Condition Routing Register 1 LSUICRR1 LSU Module Interrupt Condition Routing Register 1 LSUICRR1LSU Module Interrupt Condition Routing Register 2 LSUICRR2 LSU Module Interrupt Condition Routing Register 2 LSUICRR2LSU Module Interrupt Condition Routing Register 3 LSUICRR3 LSU Module Interrupt Condition Routing Register 3 LSUICRR3Errrstevnticrr Errrstevnticrr Field DescriptionsERRRSTEVNTICRR2 Field Descriptions ICR11ERRRSTEVNTICRR3 ERRRSTEVNTICRR3 Field DescriptionsINTDSTn Interrupt Status Decode Registers INTDSTnDECODE INTDSTn Interrupt Status Decode Registers INTDSTnDECODECountdown INTDSTn Interrupt Rate Control Registers INTDSTnRATECNTLCountdownvalue ValueAddressmsb LSUn Control Register 0 LSUnREG0LSU n Control Register 0 LSU nREG0 Field Descriptions Bit Ext address fieldsLSUn Control Register 1 LSUnREG1 AddresslsbconfigoffsetAddresslsb Configoffse T LSU n Control Register 1 LSU nREG1 Field DescriptionsDspaddress LSUn Control Register 2 LSUnREG2LSU n Control Register 2 LSU nREG2 Field Descriptions 32b DSP byte addressLSUn Control Register 3 LSUnREG3 LSU n Control Register 3 LSU nREG3 Field DescriptionsBytecount LSUn Control Register 4 LSUnREG4 LSUn Control Register 4 LSUnREG4 Field DescriptionsDrbllinfo LSUn Control Register 5 LSUnREG5LSU n Control Register 5 LSU nREG5 Field Descriptions Hopcount PackettypeCompletioncode BSY LSUn Control Register 6 LSUnREG6LSUn Control Register 6 LSUnREG6 Field Descriptions CompletioncLSU Congestion Control Flow Mask n Lsuflowmasks n FlowmaskTxhdp Txcp Rxhdp Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACPTransmit Queue Teardown Register Txqueueteardown QUEUE5FLOWMASK QUEUE4FLOWMASK QUEUE1FLOWMASK QUEUE0FLOWMASKQUEUE3FLOWMASK QUEUE2FLOWMASK QUEUE7FLOWMASK QUEUE6FLOWMASKQUEUE15FLOWMASK QUEUE14FLOWMASK MaskReceive Queue Teardown Register Rxqueueteardown Receive Queue Teardown Register RxqueueteardownReceive Cppi Control Register Rxcppicntl Receive Cppi Control Register Rxcppicntl Field Descriptions3QUEUEPTR Txqueuemap3NUMMSGS 2NUMMSGS6NUMMSGS 7NUMMSGS7QUEUEPTR 6QUEUEPTR10NUMMSGS 11NUMMSGS11QUEUEPTR 10QUEUEPTR14NUMMSGS 15NUMMSGS15QUEUEPTR 14QUEUEPTRMailbox-to-Queue Mapping Register Ln RXUMAPLn Mailbox-to-Queue Mapping Register Hn RXUMAPHn Flow Control Table Entry Registers FLOWCNTLn FlowcntlidDevice Identity CAR Devid Device Identity CAR Devid Field DescriptionsDevicerev Device Information CAR DevinfoDevice Information CAR Devinfo Field Descriptions Vendor supply device revisionAssembly Identity CAR Asblyid Assembly Identity CAR Asblyid Field DescriptionsAssembly Information CAR Asblyinfo Assembly Information CAR Asblyinfo Field DescriptionsProcessing Element Features CAR Pefeat Processing Element Features CAR Pefeat Field DescriptionsSource Operations CAR Srcop Source Operations CAR Srcop Field DescriptionsDestination Operations CAR Destop Destination Operations CAR Destop Field DescriptionsIngcontrol Processing Element Logical Layer Control CSR PellctlExtendedaddress RessingcontLocal Configuration Space Base Address 0 CSR Lclcfghbar LcsbaLocal Configuration Space Base Address 1 CSR Lclcfgbar Local Configuration Space Base Address 1 CSR LclcfgbarBase Device ID CSR Baseid Base Device ID CSR Baseid Field DescriptionsHostbasede Host Base Device ID Lock CSR HostbaseidlockHostbasedeviceid ViceidComponent Tag CSR Comptag Component Tag CSR Comptag Field DescriptionsComponenttag Efptr EfidPort Link Timeout Control CSR Spltctl Field Descriptions Port Link Time-Out Control CSR SpltctlPort Response Time-Out Control CSR Sprtctl Port Response Time-Out Control CSR SprtctlPort General Control CSR Spgenctl Port General Control CSR Spgenctl Field DescriptionsPort Link Maintenance Request CSR n SPnLMREQ CommandPort Link Maintenance Response CSR n SPnLMRESP Port Local AckID Status CSR n SPnACKIDSTAT Port Error and Status CSR n SPnERRSTAT Port Error and Status CSR n SPnERRSTAT Field DescriptionsPortok PortuninitiaLized Port Control CSR n SPnCTL Port Control CSR n SPnCTL Field DescriptionsPort Control CSR n SP nCTL Field Descriptions NableError Reporting Block Header Errrptbh Error Reporting Block Header Errrptbh Field DescriptionsLogical/Transport Layer Error Detect CSR Errdet Logical/Transport Layer Error Enable CSR Erren Logical/Transport Layer High Address Capture CSR Haddrcapt ADDRESS633250 bit addresses Logical/Transport Layer Address Capture CSR Addrcapt ADDRESS313Xamsbs Msbsourceid Sourceid Logical/Transport Layer Device ID Capture CSR IdcaptMsbdestid Destid MsbdestidImpspecific Logical/Transport Layer Control Capture CSR CtrlcaptFtype Ttype Msginfo FtypeDeviceidmsb Port-Write Target Device ID CSR PwtgtidPort-Write Target Device ID CSR Pwtgtid Field Descriptions DeviceidPort Error Detect CSR n SPnERRDET Port Error Detect CSR n SPnERRDET Field DescriptionsPort Error Rate Enable CSR n SPnRATEEN Port Error Rate Enable CSR n SPnRATEEN Field DescriptionsPort n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0 CAPTURE0 CAPTURE0CAPTURE1 CAPTURE1CAPTURE2 CAPTURE2CAPTURE3 CAPTURE3Port Error Rate CSR n SPnERRRATE Port Error Rate CSR n SPnERRRATE Field DescriptionsPort Error Rate Threshold CSR n SPnERRTHRESH Pwtimer Port IP Discovery Timer in 4x mode SpipdiscoverytimerDiscoverytimer DiscoverytiPort IP Mode CSR Spipmode Port IP Mode CSR Spipmode Field DescriptionsPort IP Mode CSR Spipmode Field Descriptions RstenSerial Port IP Prescalar Ipprescal Serial Port IP Prescalar Ipprescal Field DescriptionsPrescale Port-Write-In Capture CSR n SPIPPWINCAPTn PwcaptPort Reset Option CSR n SPnRSTOPT Port Reset Option CSR n SP nRSTOPT Field DescriptionsPortid Port Control Independent Register n SPnCTLINDEP Maxretryth MaxretryenMaxretryer IrqenPort Silence Timer n SPnSILENCETIMER Port Silence Timer n SPnSILENCETIMER Field DescriptionsSilencetimer Multevntcs MultevntcsPort Control Symbol Transmit n SPnCSTX Port Control Symbol Transmit n SP nCSTX Field DescriptionsImportant Notice