Texas Instruments TMS320C645x manual TXQueueMap10 2316 0x0A

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SRIO Functional Description

Table 21. Weighted Round Robin Programming Registers (Address Offset 0x7E0 – 0x7EC)

(continued)

Name	Bit	Access	Reset Value	Description
TX_Queue_Map10	[23:16]	R/W	0x0A	[23:20] = Number of contiguous messages (descriptors) to process before
				moving to TX_Queue_Map11
				[19:16] = Pointer to a Queue, programmable to any of the 16 TX queues
TX_Queue_Map11	[31:24]	R/W	0x0B	[31:28] = Number of contiguous messages (descriptors) to process before
				moving to TX_Queue_Map12
				[27:24] = Pointer to a Queue, programmable to any of the 16 TX queues
TX_Queue_Map12	[7:0]	R/W	0x0C	[7:4] = Number of contiguous messages (descriptors) to process before
				moving to TX_Queue_Map13
				[3:0] = Pointer to a Queue, programmable to any of the 16 TX queues
TX_Queue_Map13	[15:8]	R/W	0x0D	[15:12] = Number of contiguous messages (descriptors) to process before
				moving to TX_Queue_Map14
				[11:8] = Pointer to a Queue, programmable to any of the 16 TX queues
TX_Queue_Map14	[23:16]	R/W	0x0E	[23:20] = Number of contiguous messages (descriptors) to process before
				moving to TX_Queue_Map15
				[19:16] = Pointer to a Queue, programmable to any of the 16 TX queues
TX_Queue_Map15	[31:24]	R/W	0x0F	[31:28] = Number of contiguous messages (descriptors) to process before
				moving to TX_Queue_Map0
				[27:24] = Pointer to a Queue, programmable to any of the 16 TX queues

The TX queues are treated differently than the RX queues. A TX queue can mix single and multi-segment message buffer descriptors. The software manages the queue usage.

All outgoing message segments have responses that indicate the status of the transaction. Responses may indicate DONE, ERROR or RETRY. A buffer descriptor may be released back to CPU control (OWNERSHIP = 0), only after all segment responses are received, or alternatively if a response timeout occurs. Timeouts and response evaluation have high priority in the state-machine since they are the only means to release TX packet resources. The CC is set in the buffer descriptor to indicate the response status to the CPU. If there is a RETRY response, the TX CPPI module will immediately retry the packet before continuing to the next queue in the round-robin, as long as the RETRY_COUNT is not exceeded. Once this limit is exceeded, the buffer can be released back to CPU control with the appropriate CC set. Retry of a message segment does not imply retrying a whole message. Only segments for which a RETRY response is received should be re-transmitted. This will involve calculating the correct starting point within the TX data buffer based on the failed segment number and message length. To achieve respectable performance, the peripheral must not wait for a message/segment response before sending out the next packet.

Since RapidIO allows for out-of-order responses, the TX CPPI hardware must support this functionality. As responses are received, the hardware updates the corresponding TX buffer descriptor to reflect the status. However, if the response is out-of-order, the hardware does not update the CP or set the corresponding interrupt. Only after all preceding outstanding message responses are received, will the CP and interrupt be updated. This ensures that a contiguous block of buffer descriptors, starting at the oldest outstanding descriptor, has been processed by the hardware and is ready for the CPU to reclaim the buffers.

A transaction timeout is used by all outgoing message and directIO packets. It is defined by the 24-bit value in the Port Response Time-out CSR. The RapidIO specification states that the maximum time interval (all 1s) is between 3 and 6 seconds. A logical layer timeout occurs if the response packet is not received before a countdown timer (initialized to this CSR value) reaches zero. Since transaction responses can be acknowledged out-of-order, a timer is needed for each supported outstanding packet in the TX queue. Each outstanding packet response timer requires a 4-bit register. The register is loaded with the current timecode when the transaction is sent. Each time the timecode changes, a 4-bit compare is done to the 16 outstanding packet registers. If the register becomes equal to the timecode again, without a response being seen, then the transaction has timed out and the buffer descriptor is written.

SPRU976 –March 2006 Serial RapidIO (SRIO) 53

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