Texas Instruments TMS320C645x Message Passing Software Requirements, RX Operation, TX Operation

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SRIO Functional Description

The CPPI module can be powered down if the message passing protocol is not being supported in the application. For example, if the direct I/O protocol is being used for data transfers, powering down the CPPI module will save power. In this situation, the buffer descriptor queue SRAMs and mailbox mapper logic should be powered down. Clocks should be gated to these blocks while in the power down state. Section 2.3.9 describes this in detail.

2.3.4.5Message Passing Software Requirements

Software performs the following functions for messaging:

RX Operation

∙Assigns Mailbox-to-queue mapping and allowable SourceIDs/mailbox- Queue Mapping

∙Sets up associated buffer descriptor memory – CPPI RAM or L2 RAM

∙Link-lists the buffer descriptors, next_descriptor_pointer

∙Assigns single segment (256B payload) and multi-segment (4KB payload) buffers to queues buffer_length

∙Assigns buffer descriptor to data buffer, buffer_pointer

∙Gives control of the buffer to the peripheral, ownership = 1

Configures and initiates RX queues

∙Assigns Head Descriptor Pointer, HDP, for up to 16 queues: RX DMA State HDP

∙Port begins to consume buffers beginning with HDP descriptor and sets ownership = 0 for each buffer descriptor used. Writes Completion Pointer, CP, RX DMA State CP and moves to next buffer.

∙Port hardware generates pending interrupt when CP is written. Physical interrupt generated when Interrupt Pacing Count down timer = 0.

Processes interrupt

∙Determines ICSR bit and process corresponding queue until ownership = 1 or eoq = 1

∙Sets processed buffer descriptor ownership = 1

∙Writes CP value of last buffer descriptor processed

∙Port hardware clears ICSR bit only if the CP value written by CPU equals port written value in the RX DMA State CP register

∙Resets interrupt pacing value

TX Operation

Sets up associated buffer descriptor memory – CPPI RAM or L2 RAM

∙Link-lists the buffer descriptors, next_descriptor_pointer

∙Assigns buffer descriptor to data buffer, buffer_pointer

∙Gives control of the buffer to the CPU, ownership = 0

∙CPU writes buffer descriptors beginning with HDP descriptor and sets ownership = 1 for each used

∙Specifies RIO fields: Dest_id, Pri, tt, Mailbox

∙Sets parameters: PortID, Message_length

∙Port starts queue transmit on CPU write to HDP for up to 16 queues - TX DMA State HDP

∙Port processes corresponding queues until ownership = 0 or next_descriptor_pointer = all 0s. Port sets eoq = 1 and writes all 0s to the HDP.

∙When each packet transmission is complete, the port sets ownership = 0 and issues an interrupt to the CPU by writing the last processed buffer descriptor address to the CP, TX DMA State CP

Processes interrupt

∙The CPU processes the buffer queue to reclaim buffers. If ownership = 0, the packet has been transmitted and the buffer is reclaimed.

∙CPU processes the queue until eoq = 1 or ownership = 1

∙CPU determines all packets have been transmitted if ownership = 0, eoq = 1, and next_descriptor_pointer = all 0s in last processed buffer descriptor

∙CPU acknowledges the interrupt after re-claiming all available buffer descriptors.

∙CPU acknowledges the interrupt by writing the CP value

SPRU976 –March 2006 Serial RapidIO (SRIO) 55

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