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SRIO Registers
5.4Peripheral Settings Control Register (PER_SET_CNTL)
Figure 60. Peripheral Settings Control Register (PER_SET_CNTL)
| 26 | 25 | 24 |
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| Reserved | SW_M | LOOP | BOOT | Reserved | TX_PRI2_WM | TX_PRI1_WM | ||
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| EM_S BACK _COM |
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| LEEP_ |
| PLETE |
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| OVER |
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| RIDE |
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| RW- | RW- | RW- |
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| 0x01 | 0x00 | 0x00 |
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LEGEND: R = Read only; |
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15 |
| 8 | 3 | 2 | 1 | 0 | |||
TX_P | TX_PRI0_WM | CBA_TRANS_PRI | 1X_M | PRESCALER_SELECT | ENPLL | ENPLL | ENPLL | ENPLL | |
RI1_W |
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| ODE |
| 4 | 3 | 2 | 1 |
M |
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RW- |
| RW- | RW- | RW- | RW- | RW- | |||
0x02 |
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| 0x00 |
| 0x00 | 0x00 | 0x00 | 0x00 |
LEGEND: R = Read only;
Table 31. Peripheral Settings Control Register (PER_SET_CNTL) Field Descriptions
Bit | Field | Value | Description |
Reserved |
| Reserved | |
26 | SW_MEM_SLEE |
| Software Memory Sleep Override |
| P_OVERRIDE | 0b | Memories are put in sleep mode while in shutdown |
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| 1b | Memories are not put in sleep mode while in shutdown |
25 | LOOPBACK |
| Loopback mode. |
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| 0b | Normal operation |
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| 1b | Loop back mode. Transmit data to receive on the same port. Packet data is looped back in the |
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| digital domain before the SERDES macros. |
24 | BOOT_COMPLE |
| Controls ability to write any register during initialization. It also includes read only registers during |
| TE |
| normal mode of operation that have application defined reset value. |
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| 0b | Write to read only registers enabled |
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| 1b | Write to read only registers disabled. Usually the boot_complete is asserted once after reset to |
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| define power on configuration. |
Reserved |
| Reserved | |
TX_PRI2_WM |
| Transmit credit threshold. Sets the required number of logical layer TX buffers needed to send | |
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| priority 2 packets across the UDI interface. This is valid for all ports in 1X mode only. |
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| Required buffer count for transmit credit threshold 2 value (TX_PRI2_WM): |
∙ 000→8, 7, 6, 5, 4, 3, 2, 1 ∙ 001→8, 7, 6, 5, 4, 3, 2 ∙ 010→8, 7, 6, 5, 4, 3 ∙ 011→8, 7, 6, 5, 4 ∙ 100→8, 7, 6, 5 ∙ 101→8, 7, 6 ∙ 110→8, 7 ∙ 111→8
SPRU976 | Serial RapidIO (SRIO) | 101 |
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