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SRIO Registers

5.3Peripheral Control Register (PCR)

The peripheral control register (PCR) contains a bit that enables or disables the entire peripheral and one bit for every module within the peripheral where this level of control is desired. The module control bits can only be written when the peripheral itself is enabled. In addition, the PCR has emulation control bits free and soft, which control the peripheral behavior during emulation halts.

Figure 59. Peripheral Control Register (PCR)

 

31-16

 

 

 

Reserved

 

 

 

R-0x00

 

 

LEGEND: R = Read only; -n= value after reset

 

 

 

15-3

2

1

0

Reserved

PERE

SOFT

FREE

 

N

 

 

R-0x00

RW-

RW-

RW-

 

0x00

0x00

0x01

LEGEND: R = Read only; -n= value after reset

 

 

 

Table 30. Peripheral Control Register (PCR) Field Descriptions

Bit

Field

Value

Description

31-3

Reserved

 

Reserved

2

PEREN

 

Peripheral Enable. Controls the flow of data in the logical layer of the peripheral. As an initiator, it

 

 

 

will prevent TX transaction generation and as a target, it will disable incoming requests. This should

 

 

 

be the last enable bit to toggle when bringing the device out of reset to begin normal operation.

 

 

0b

Disables data flow control

 

 

1b

Enables data flow control

1

SOFT

 

Emulation Control - SOFT bit

0

FREE

 

Emulation Control - FREE bit

100

Serial RapidIO (SRIO)

SPRU976 –March 2006

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Texas Instruments TMS320C645x manual Peripheral Control Register PCR Field Descriptions, Pere Soft Free, Bit Field