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SRIO Registers
5.3Peripheral Control Register (PCR)
The peripheral control register (PCR) contains a bit that enables or disables the entire peripheral and one bit for every module within the peripheral where this level of control is desired. The module control bits can only be written when the peripheral itself is enabled. In addition, the PCR has emulation control bits free and soft, which control the peripheral behavior during emulation halts.
Figure 59. Peripheral Control Register (PCR)
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| Reserved |
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LEGEND: R = Read only; |
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2 | 1 | 0 | |
Reserved | PERE | SOFT | FREE |
| N |
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RW- | RW- | RW- | |
| 0x00 | 0x00 | 0x01 |
LEGEND: R = Read only; |
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Table 30. Peripheral Control Register (PCR) Field Descriptions
Bit | Field | Value | Description |
Reserved |
| Reserved | |
2 | PEREN |
| Peripheral Enable. Controls the flow of data in the logical layer of the peripheral. As an initiator, it |
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| will prevent TX transaction generation and as a target, it will disable incoming requests. This should |
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| be the last enable bit to toggle when bringing the device out of reset to begin normal operation. |
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| 0b | Disables data flow control |
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| 1b | Enables data flow control |
1 | SOFT |
| Emulation Control - SOFT bit |
0 | FREE |
| Emulation Control - FREE bit |
100 | Serial RapidIO (SRIO) | SPRU976 |