Block n Enable Register BLKnEN | Texas Instruments TMS320C645x

www.ti.com

SRIO Registers

5.7Block n Enable Register (BLKn_EN)

There are nine of these registers, one for each of nine logical blocks in the peripheral.

Figure 63. Block n Enable Register (BLKn_EN)

31-16
Reserved
R-0x00
LEGEND: R = Read only; -n= value after reset
15-1	0
Reserved	EN
R-0x00	RW-
	Undefi
	ned
LEGEND: R = Read only; -n= value after reset

Table 34. Block n Enable Register (BLKn_EN) Field Descriptions

Bit	Field	Value	Description
31-1	Reserved		Reserved
0	EN		Controls reset to nth (0 to 8) clock/logical domain.
		0	Logical block n disabled (held in reset, clocks disabled)
		1	Logical block n enabled

106

Serial RapidIO (SRIO)

SPRU976 –March 2006

Submit Documentation Feedback

Image 106

Texas Instruments TMS320C645x manual Block n Enable Register BLKnEN Field Descriptions

Contents

Users Guide Submit Documentation Feedback Contents Errrstevnticrr Base Device ID CSR Baseid List of Figures Load/Store Module Interrupt Condition Routing Registers 150 Port Error Rate Threshold CSR n SP n Errthresh List of Tables LSUn Control Register 0 LSUnREG0 Field Descriptions Base Device ID CSR Baseid Field Descriptions Read This First General RapidIO System RapidIO Architectural Hierarchy Overview RapidIO Interconnect Architecture 3 1x/4x LP-Serial RapidIO Feature Support in Srio Features Supported in Srio External Devices Requirements Features Not SupportedStandards RapidIO Documents and Links Overview Peripheral Data Flow Srio Packets Operation Sequence Operation Sequence Example Packet Streaming Write Control Symbols 4x RapidIO Packet Data Stream Streaming-Write Class Packet Type Srio Packet Ftype/TtypeFtype Ttype Packet Type Functional Operation Srio PinsBlock Diagram Pin Description Srio Conceptual Block Diagram Bits of Serdescfg nCNTL Register 0x120 0x12c Serdes and its ConfigurationsEnabling the PLL Bit Name Value Description Line Rate versus PLL Output Clock Frequency Bits of Serdescfg nCNTL Register 0x120 0x12cRate Bit Effects Enabling the Receiver Frequency Range versus MPYBits of Serdescfgrx nCNTL Registers Bits of SERDESCFGRXnCNTL Registers Disabled. Loss of signal detection disabledBit Field Value Description 1514 Bits of Serdescfgtx nCNTL Registers EQ BitsEnabling the Transmitter CFGRX2219 Low Freq Gain Swing Bits Bits of Serdescfgtx nCNTL RegistersDE Bits Serdes Configuration Example DirectIO Control/Command Register Field Mapping RapidIO Packet Header Field Status Field Function Control/Command Register RapidIO Packet Header FieldStatus Fields BSY LSU Registers Timing Example Burst Nwriter Detailed Data Path Description TX Operation Write Transactions Read Transactions Segmentation RX Operation Reset and Power Down State Message Passing Cppi RX Scheme for RapidIO Queue Mapping Table Address Offset 0x0800 0x08FC Queue Mapping Register Rxumapl n Bit Name Description RX Buffer Descriptor Fields RX Buffer Descriptor Field Descriptions Field Description RX Buffer Descriptor Field Descriptions Field Description RX Cppi Mode Explanation Cppi Boundary Diagram TX Buffer Descriptor Fields TX Buffer Descriptor Field Definitions Uses this bit to reclaim buffers Ssize TXQUEUECNTL1- Address Offset 0x7E4 Name Bit Access Reset Value DescriptionTXQUEUECNTL0- Address Offset 0x7E0 TXQUEUECNTL2- Address Offset 0x7E8 TXQueueMap10 2316 0x0A Detailed Data Path Description RX Operation Message Passing Software RequirementsTX Operation Queue Mapping Initialization ExampleRX Buffer Descriptor TX Buffer Descriptor NDP Maintenance Start Message Passing Doorbell Doorbell Operation Congestion Control Detailed Description Name Bit Transmit Source Flow Control Masks Configuration Bus Example Endianness Reset DMA Example Enable and Enable Status Registers Reset SummaryBLK8ENSTA BLK7ENSTA Gblen Enable and Enable Status Bit Field DescriptionsEnstat BLK0EN BLK2EN BLK1ENBLK1ENSTAT BLK2ENSTAT BLK8ENSTAT Software Shutdown DetailsEmulation Peren Soft Free Enabling the Srio Peripherals Emulation Control SignalsPeren Peripheral Initializations 11.2 PLL, Ports, Device ID and Data Rate InitializationsSet Device ID Registers Assert the Peren bit to enable logical layer data flow Read register to check portx1-4 OK bit Bootload Data Movement Bootload CapabilityConfiguration Device Wakeup MSG REQ ERR CPU Interrupts General Description Interrupt Condition Control Registers Interrupt Source Configuration Options Where ICS0 Doorbell1, bit 0, through ICS15 Doorbell1, bit Interrupt Conditions LSU Interrupt Condition Clear Registers Iccr Address Offset ICC11 ICC10 ICC9 ICC8 ICS11 ICS10 ICS9 ICS8ICS2 ICS1 ICS0 ICC2 ICC1 ICC0 Interrupt Condition Routing Options DOORBELL0ICRR2 Address Offset LSUICRR2 Address Offset 0x02E8 LSUICRR1 Address Offset 0x02E4LSUICRR3 Address Offset 0x02EC ERRRSTEVNTICRR3 Address Offset 0x02F8 Interrupt Status Decode RegistersERRRSTEVNTICRR2 Address Offset 0x02F4 ICR2 ICR1 ICR0 Sharing of Isdr Bits Interrupt Pacing Interrupt GenerationISDR3 ISDR2 ISDR1 ISDR9 ISDR8 ISDR7 ISDR6 ISDR5 ISDR4 ISDR0 Interrupt Handling INTDSTnRATECNTL Interrupt Rate Control Register Interrupt Conditions Serial Rapid IO Srio Registers IntroductionOffset Acronym Register Description Serial Rapid IO Srio Registers Offset Acronym Register Description RR2 LSUICRR3Errrstevntic RR3 LSU3REG1 QUEUE3TXDMAC QUEUE1TXDMACQUEUE2TXDMAC QUEUE4TXDMAC QUEUE12RXDMA SKS7 TxcppiflowmaSKS6 Rxqueuetear RXUMAPL19 RXUMAPL18RXUMAPH18 RXUMAPH19 Pefeat AsblyidAsblyinfo Srcop SP0ERRCAPTDB SP0ERRATTRCAPTDBG0 SP0ERRRATE SP3ERRTHRESH TimerSP3ERRRATE Spipdiscovery Type Peripheral Identification Register PIDPeripheral ID Register PID Field Descriptions Class REV Pere Soft Free Peripheral Control Register PCRPeripheral Control Register PCR Field Descriptions Bit Field Peripheral Settings Control Register Persetcntl Prescalerse Cbatranspr1XMODE Lect ENPLL2 ENPLL3ENPLL1 Peripheral Global Enable Register Gblen Peripheral Global Enable Register Gblen Field Descriptions ENS Peripheral Global Enable Status Register GblenstatGBL TAT Block n Enable Register BLKnEN Block n Enable Register BLKnEN Field Descriptions Block n Enable Status Register BLKnENSTAT Block n Enable Status Register BLKnENSTAT 8BNODEID RapidIO DEVICEID1 Register DEVICEIDREG1RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions 16BNODEID RapidIO DEVICEID2 Register DEVICEIDREG2 RapidIO DEVICEID2 Register DEVICEIDREG2 Field Descriptions Packet Forwarding Register n for 16b DeviceIDs PF16BCNTLn Packet Forwarding Register n for 8b DeviceIDs PF8BCNTLn CDR LOS Align Term Invpa Rate Buswidth CFGRX2219 Low Freq Gain Zero Freq at e28 min Swing Invpa Rate Buswidth EnftEntx CFGTX119 Amplitude mV dfpp Swing BitsDE Bits CFGTX1512 Amplitude Reduction RIOCLK/RIOCLK Serdes Macro Configuration Register n SERDESCFGnCNTLMPY Enpll MPY DOORBELLn Interrupt Status Register DOORBELLnICSR DOORBELLn Interrupt Status Register DOORBELLnICSR DOORBELLn Interrupt Clear Register DOORBELLnICCR DOORBELLn Interrupt Clear Register DOORBELLnICCR RX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Clear Register Rxcppiiccr RX Cppi Interrupt Clear Register Rxcppiiccr TX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Clear Register Txcppiiccr TX Cppi Interrupt Clear Register Txcppiiccr LSU Status Interrupt Register Lsuicsr Field Descriptions LSU Status Interrupt Register LsuicsrICS31-0 Load/Store module interrupt condition status bits LSU Clear Interrupt Register LSU Iccr Field Descriptions LSU Clear Interrupt Register LSU IccrICS31-0 Load/Store module interrupt clear bits 31-17 126 DOORBELLn Interrupt Condition Routing Register DOORBELLnICRR 128 RX Cppi Interrupt Condition Routing Register Rxcppi Icrr ICR RX Cppi Interrupt condition routing bits RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2 RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2 TX Cppi Interrupt Condition Routing Register Txcppi Icrr ICR TX Cppi Interrupt condition routing bits TX Cppi Interrupt Condition Routing Register Txcppi ICRR2 TX Cppi Interrupt Condition Routing Register Txcppi ICRR2 LSU Module Interrupt Condition Routing Register 0 LSUICRR0 ICR LSU Module Interrupt Condition Routing Register 1 LSUICRR1 LSU Module Interrupt Condition Routing Register 1 LSUICRR1 LSU Module Interrupt Condition Routing Register 2 LSUICRR2 LSU Module Interrupt Condition Routing Register 2 LSUICRR2 LSU Module Interrupt Condition Routing Register 3 LSUICRR3 LSU Module Interrupt Condition Routing Register 3 LSUICRR3 Errrstevnticrr Errrstevnticrr Field Descriptions ERRRSTEVNTICRR2 Field Descriptions ICR11 ERRRSTEVNTICRR3 ERRRSTEVNTICRR3 Field Descriptions INTDSTn Interrupt Status Decode Registers INTDSTnDECODE INTDSTn Interrupt Status Decode Registers INTDSTnDECODE Countdown INTDSTn Interrupt Rate Control Registers INTDSTnRATECNTLCountdownvalue Value Addressmsb LSUn Control Register 0 LSUnREG0LSU n Control Register 0 LSU nREG0 Field Descriptions Bit Ext address fields LSUn Control Register 1 LSUnREG1 AddresslsbconfigoffsetAddresslsb Configoffse T LSU n Control Register 1 LSU nREG1 Field Descriptions Dspaddress LSUn Control Register 2 LSUnREG2LSU n Control Register 2 LSU nREG2 Field Descriptions 32b DSP byte address LSU n Control Register 3 LSU nREG3 Field Descriptions LSUn Control Register 3 LSUnREG3Bytecount LSUn Control Register 4 LSUnREG4 LSUn Control Register 4 LSUnREG4 Field Descriptions Drbllinfo LSUn Control Register 5 LSUnREG5LSU n Control Register 5 LSU nREG5 Field Descriptions Hopcount Packettype Completioncode BSY LSUn Control Register 6 LSUnREG6LSUn Control Register 6 LSUnREG6 Field Descriptions Completionc LSU Congestion Control Flow Mask n Lsuflowmasks n Flowmask Txhdp Txcp Rxhdp Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP Transmit Queue Teardown Register Txqueueteardown QUEUE5FLOWMASK QUEUE4FLOWMASK QUEUE1FLOWMASK QUEUE0FLOWMASKQUEUE3FLOWMASK QUEUE2FLOWMASK QUEUE7FLOWMASK QUEUE6FLOWMASK QUEUE15FLOWMASK QUEUE14FLOWMASK Mask Receive Queue Teardown Register Rxqueueteardown Receive Queue Teardown Register Rxqueueteardown Receive Cppi Control Register Rxcppicntl Receive Cppi Control Register Rxcppicntl Field Descriptions 3QUEUEPTR Txqueuemap3NUMMSGS 2NUMMSGS 6NUMMSGS 7NUMMSGS7QUEUEPTR 6QUEUEPTR 10NUMMSGS 11NUMMSGS11QUEUEPTR 10QUEUEPTR 14NUMMSGS 15NUMMSGS15QUEUEPTR 14QUEUEPTR Mailbox-to-Queue Mapping Register Ln RXUMAPLn Mailbox-to-Queue Mapping Register Hn RXUMAPHn Flow Control Table Entry Registers FLOWCNTLn Flowcntlid Device Identity CAR Devid Device Identity CAR Devid Field Descriptions Devicerev Device Information CAR DevinfoDevice Information CAR Devinfo Field Descriptions Vendor supply device revision Assembly Identity CAR Asblyid Assembly Identity CAR Asblyid Field Descriptions Assembly Information CAR Asblyinfo Assembly Information CAR Asblyinfo Field Descriptions Processing Element Features CAR Pefeat Processing Element Features CAR Pefeat Field Descriptions Source Operations CAR Srcop Source Operations CAR Srcop Field Descriptions Destination Operations CAR Destop Destination Operations CAR Destop Field Descriptions Ingcontrol Processing Element Logical Layer Control CSR PellctlExtendedaddress Ressingcont Local Configuration Space Base Address 0 CSR Lclcfghbar Lcsba Local Configuration Space Base Address 1 CSR Lclcfgbar Local Configuration Space Base Address 1 CSR Lclcfgbar Base Device ID CSR Baseid Base Device ID CSR Baseid Field Descriptions Hostbasede Host Base Device ID Lock CSR HostbaseidlockHostbasedeviceid Viceid Component Tag CSR Comptag Field Descriptions Component Tag CSR ComptagComponenttag Efptr Efid Port Link Timeout Control CSR Spltctl Field Descriptions Port Link Time-Out Control CSR Spltctl Port Response Time-Out Control CSR Sprtctl Port Response Time-Out Control CSR Sprtctl Port General Control CSR Spgenctl Port General Control CSR Spgenctl Field Descriptions Port Link Maintenance Request CSR n SPnLMREQ Command Port Link Maintenance Response CSR n SPnLMRESP Port Local AckID Status CSR n SPnACKIDSTAT Port Error and Status CSR n SPnERRSTAT Port Error and Status CSR n SPnERRSTAT Field Descriptions Portuninitia PortokLized Port Control CSR n SPnCTL Port Control CSR n SPnCTL Field Descriptions Port Control CSR n SP nCTL Field Descriptions Nable Error Reporting Block Header Errrptbh Error Reporting Block Header Errrptbh Field Descriptions Logical/Transport Layer Error Detect CSR Errdet Logical/Transport Layer Error Enable CSR Erren ADDRESS6332 Logical/Transport Layer High Address Capture CSR Haddrcapt50 bit addresses ADDRESS313 Logical/Transport Layer Address Capture CSR AddrcaptXamsbs Msbsourceid Sourceid Logical/Transport Layer Device ID Capture CSR IdcaptMsbdestid Destid Msbdestid Impspecific Logical/Transport Layer Control Capture CSR CtrlcaptFtype Ttype Msginfo Ftype Deviceidmsb Port-Write Target Device ID CSR PwtgtidPort-Write Target Device ID CSR Pwtgtid Field Descriptions Deviceid Port Error Detect CSR n SPnERRDET Port Error Detect CSR n SPnERRDET Field Descriptions Port Error Rate Enable CSR n SPnRATEEN Port Error Rate Enable CSR n SPnRATEEN Field Descriptions Port n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0 CAPTURE0 CAPTURE0 CAPTURE1 CAPTURE1 CAPTURE2 CAPTURE2 CAPTURE3 CAPTURE3 Port Error Rate CSR n SPnERRRATE Port Error Rate CSR n SPnERRRATE Field Descriptions Port Error Rate Threshold CSR n SPnERRTHRESH Pwtimer Port IP Discovery Timer in 4x mode SpipdiscoverytimerDiscoverytimer Discoveryti Port IP Mode CSR Spipmode Port IP Mode CSR Spipmode Field Descriptions Port IP Mode CSR Spipmode Field Descriptions Rsten Serial Port IP Prescalar Ipprescal Field Descriptions Serial Port IP Prescalar IpprescalPrescale Port-Write-In Capture CSR n SPIPPWINCAPTn Pwcapt Port Reset Option CSR n SP nRSTOPT Field Descriptions Port Reset Option CSR n SPnRSTOPTPortid Port Control Independent Register n SPnCTLINDEP Maxretryth MaxretryenMaxretryer Irqen Port Silence Timer n SPnSILENCETIMER Field Descriptions Port Silence Timer n SPnSILENCETIMERSilencetimer Multevntcs Multevntcs Port Control Symbol Transmit n SPnCSTX Port Control Symbol Transmit n SP nCSTX Field Descriptions Important Notice