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SRIO Registers
5.108 Port Control Independent Register n (SPn_CTL_INDEP)
Each of the four ports is supported by a register of this type.
Figure 164. Port Control Independent Register n (SPn_CTL_INDEP)
31 | 30 | 29 | 26 | 23 | 22 | 21 | 20 | 17 | 16 | |||
Reserv | TX_FL | SOFT | Reserved | FORC | TRANS_MODE | DEBU | SEND | ILL_T | ILL_T | Reserved | MAX_ | MAX_ |
ed | W | _REC |
| E_REI |
| G | _DBG | RANS | RANS |
| RETR | RETR |
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| NIT |
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| _PKT | _EN | _ERR |
| Y_EN Y_ER | |
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| R |
R- | RW- | RW- | W- | RW- | RW- | RW- | RC- | RW- | RC- | |||
0x00 | 0x00 | 0x00 |
| 0x00 |
| 0x00 | 0x00 | 0x00 | 0x00 |
| 0x00 | 0x00 |
LEGEND: R = Read only; |
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| 7 | 6 |
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| MAX_RETRY_THR |
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| IRQ_E | IRQ_E |
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| Reserved |
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| N | RR |
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| RW- | RC- |
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| 0x00 | 0x00 |
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LEGEND: R = Read only;
Table 138. Port Control Independent Register n (SPn_CTL_INDEP) Field Descriptions
Bit | Field | Value | Description | |
31 | Reserved |
| Reserved | |
30 | TX_FLW |
| Transmit Link Flow Control enable | |
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| 0b | Disables transmit flow control (Enables receive link flow control) | |
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| 1b | Enables transmit flow control (not supported) | |
29 | SOFT_REC |
| Software controlled error recovery. | |
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| 0b | Transmission of error recovery sequence is performed by the hardware | |
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| 1b | Transmission of error recovery sequence is performed by the software. By default the transmission | |
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| error recovery sequence is performed by the hardware. If this bit is set, the hardware recovery is | |
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| disabled and the hardware transmission logic must wait until software has written the register Port n | |
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| Local ackID Status CSR. | |
Reserved |
| Reserved | ||
26 | FORCE_REINIT |
| Force reinitialization process. In 4x mode this bit affects all 4 lanes. This bit is write only, read | |
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| always "0". | |
| Describes the transfer mode for each port. | |||
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| 00 | Reserved | |
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| 01 | Store & Forward Mode | |
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| 1x | Reserved | |
23 | DEBUG |
| Mode of operation. | |
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| 0b | Normal mode | |
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| 1b | Debug mode. The debug mode unlocks capture registers for write and enable debug packet | |
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| generator feature. | |
22 | SEND_DBG_PKT |
| Send debug packet. Write 1 force to send debug packet. This bit is set by software and cleared | |
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| after debug packet is sent. Writes when the bit is set are ignored. Debug mode only. | |
21 | ILL_TRANS_EN |
| Illegal Transfer Error reporting Enable. If enabled, the | |
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| 0b | Disables Illegal Transfer Error reporting | |
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| 1b | Enables Illegal Transfer Error reporting | |
20 | ILL_TRANS_ERR |
| Illegal Transfer Error. It is set to 1 as following: | |
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| ∙ | Received transaction has reserved tt field |
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| ∙ | Reserved field of Maintenance transaction type |
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| ∙ | DestID is not defined in |
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| Once set, it remains set until written with logic 1 to clear. This bit also is cleared by writing all 0s to | |
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| the register SP0_ERR_DET. This error is also reported in registers SP0_ERR_DET and ERR_DET. | |
Reserved |
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SPRU976 | Serial RapidIO (SRIO) | 213 |
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