Texas Instruments TMS320C645x manual LSU Interrupt Condition Clear Registers Iccr Address Offset

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Interrupt Conditions

Where ICS0 - TX CPPI interrupt, buffer descriptor queue 0, through ICS15 - TX CPPI interrupt, buffer descriptor queue 15.

Clearing of any ICSR bit is dependent on the CPU writing to the TX DMA State CP. The CPU acknowledges the interrupt after reclaiming all available buffer descriptors by writing the CP value. This value is compared against the port written value in the TX DMA State CP register. If equal, the interrupt is deasserted.

Figure 49. LSU Load/Store Module Interrupts

LSU Interrupt Condition Status Registers (ICSR) (Address Offset 0x0260)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

ICS31

ICS30

ICS29

ICS28

ICS27

ICS26

ICS25

ICS24

ICS23

ICS22

ICS21

ICS20

ICS19

ICS18

ICS17

ICS16

R/W-0 R/W-0 R/W-0

R/W-0 R/W-0 R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0 R/W-0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ICS15

ICS14

ICS13

ICS12

ICS11

ICS10

ICS9

ICS8

ICS7

ICS6

ICS5

ICS4

ICS3

ICS2

ICS1

ICS0

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

R/W-0

LEGEND: R = Read, W = Write, n = value at reset

LSU Interrupt Condition Clear Registers (ICCR) (Address Offset 0x0268)

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

ICC31

ICC30

ICC29

ICC28

ICC27

ICC26

ICC25

ICC24

ICC23

ICC22

ICC21

ICC20

ICC19

ICC18

ICC17

ICC16

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

ICC15

ICC14

ICC13

ICC12

ICC11

ICC10

ICC9

ICC8

ICC7

ICC6

ICC5

ICC4

ICC3

ICC2

ICC1

ICC0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

W-0

LEGEND: R = Read, W = Write, n = value at reset

Where:

∙Bit 0- Transaction complete, No Errors (Posted/Non-posted), LSU1 – see note

∙Bit 1- Non-posted transaction received ERROR response, or error in response payload, LSU1

∙Bit 2- Transaction was not sent due to Xoff condition, LSU1

∙Bit 3- Transaction was not sent due to unsupported transaction type or invalid field encoding LSU1

∙Bit 4- Transaction Timeout Occurred, LSU1

∙Bit 5- Transaction was not sent due to DMA data transfer error, LSU1

∙Bit 6- Retry Doorbell response received or Atomic Test-and-swap was not allowed (semaphore in use), LSU1

∙Bit 7- Packet not sent due to unavailable outbound credit at given priority, LSU1

∙Bit 8- Transaction complete, No Errors (Posted/Non-posted), LSU2 – see note

∙Bit 9- Non-posted transaction received ERROR response, or error in response payload, LSU2

∙Bit 10- Transaction was not sent due to Xoff condition, LSU2

∙Bit 11- Transaction was not sent due to unsupported transaction type or invalid field encoding LSU2

∙Bit 12- Transaction Timeout Occurred, LSU2

∙Bit 13- Transaction was not sent due to DMA data transfer error, LSU2

∙Bit 14- Retry Doorbell response received or Atomic Test-and-swap was not allowed (semaphore in use), LSU2

∙Bit 15- Packet not sent due to unavailable outbound credit at given priority, LSU2

∙Bit 16- Transaction complete, No Errors (Posted/Non-posted), LSU3 – see note

∙Bit 17- Non-posted transaction received ERROR response, or error in response payload, LSU3

∙Bit 18- Transaction was not sent due to Xoff condition, LSU3

∙Bit 19- Transaction was not sent due to unsupported transaction type or invalid field encoding LSU3

∙Bit 20- Transaction Timeout Occurred, LSU3

SPRU976 –March 2006 Serial RapidIO (SRIO) 79

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