RapidIO Interconnect Architecture | Texas Instruments TMS320C645x

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Overview

1.1.2RapidIO Interconnect Architecture

The interconnect architecture is defined as a packet switched protocol independent of a physical layer implementation. Figure 2 illustrates the interconnection system.

Figure 2. RapidIO Interconnect Architecture

Host

Memory

Memory

Host	Host
Processor	Processor

RapidIO

RapidIO

RapidIO

Switch

I/O

	Control	ASIC/FPGA
	Processor	ASIC/FPGA
	Processor

	Memory	RapidIO
	Memory	Switch
		Switch
		RapidIO
		RapidIO
		RapidIO
		Switch

	InfiniBand™ HCA
	IO	Memory
	Processor	Memory
	Processor
	To	Area
		Network
	RapidIO
	InfiniBand

RapidIO

Backplane

RapidIO

Switch

RapidIO

DSP

DSP

DSP

DSP

			RapidIO
			RapidIO
	Memory	Comm	Memory	Comm
	Memory	Processor	Memory	Processor
		Processor		Processor
			TDM,GMII,

RapidIO

PCI

PCI

Legacy

DSP Farm

Communications

PCI

(1)InfiniBand™ is a trademark of the InfiniBand Trade Association.

1.1.31x/4x LP-Serial

Currently, there are two physical layer specifications recognized by the RapidIO Trade Association: 8/16 LP-LVDS and 1X/4X LP-Serial. The 8/16 LP-LVDS specification is a point-to-point synchronous clock sourcing DDR interface. The 1X/4X LP-Serial specification is a point-to-point, AC coupled, clock recovery interface. The two physical layer specifications are not compatible.

SRIO complies with the 1X/4X LP-Serial specification. The serializer/deserializer (SERDES) technology in SRIO also aligns with that specification.

The 1X/4X LP-Serial specification currently covers three frequency points: 1.25, 2.5, and 3.125 Gbps. This defines the total bandwidth of each differential pair of I/O signals. An 8b/10b encoding scheme ensures ample data transitions for the clock recovery circuits. Due to the 8b/10b encoding overhead, the effective data bandwidth per differential pair is 1.0, 2.0, and 2.5 Gbps respectively. Serial RapidIO only specifies these rates for both the 1X and 4X ports. A 1X port is defined as 1 TX and 1 RX differential pair. A 4X port is a combination of four of these pairs. This document describes a 4X RapidIO port that can also be configured as four 1X ports, thus providing a scalable interface capable of supporting a data bandwidth of 1 to 10 Gbps.

16

Serial RapidIO (SRIO)

SPRU976 –March 2006

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Texas Instruments TMS320C645x manual RapidIO Interconnect Architecture, 3 1x/4x LP-Serial

Contents

Users Guide Submit Documentation Feedback Contents Errrstevnticrr Base Device ID CSR Baseid List of Figures Load/Store Module Interrupt Condition Routing Registers 150 Port Error Rate Threshold CSR n SP n Errthresh List of Tables LSUn Control Register 0 LSUnREG0 Field Descriptions Base Device ID CSR Baseid Field Descriptions Read This First General RapidIO System RapidIO Architectural Hierarchy Overview RapidIO Interconnect Architecture 3 1x/4x LP-Serial RapidIO Feature Support in Srio Features Supported in Srio Features Not Supported StandardsExternal Devices Requirements RapidIO Documents and Links Overview Peripheral Data Flow Srio Packets Operation Sequence Operation Sequence Example Packet Streaming Write Control Symbols 4x RapidIO Packet Data Stream Streaming-Write Class Packet Type Srio Packet Ftype/TtypeFtype Ttype Packet Type Srio Pins Block DiagramFunctional Operation Pin Description Srio Conceptual Block Diagram Serdes and its Configurations Enabling the PLLBits of Serdescfg nCNTL Register 0x120 0x12c Bit Name Value Description Line Rate versus PLL Output Clock Frequency Bits of Serdescfg nCNTL Register 0x120 0x12cRate Bit Effects Enabling the Receiver Frequency Range versus MPYBits of Serdescfgrx nCNTL Registers Bits of SERDESCFGRXnCNTL Registers Disabled. Loss of signal detection disabledBit Field Value Description 1514 EQ Bits Enabling the TransmitterBits of Serdescfgtx nCNTL Registers CFGRX2219 Low Freq Gain Swing Bits Bits of Serdescfgtx nCNTL RegistersDE Bits Serdes Configuration Example DirectIO Control/Command Register Field Mapping RapidIO Packet Header Field Control/Command Register RapidIO Packet Header Field Status FieldsStatus Field Function BSY LSU Registers Timing Example Burst Nwriter Detailed Data Path Description TX Operation Write Transactions Read Transactions Segmentation RX Operation Reset and Power Down State Message Passing Cppi RX Scheme for RapidIO Queue Mapping Table Address Offset 0x0800 0x08FC Queue Mapping Register Rxumapl n Bit Name Description RX Buffer Descriptor Fields RX Buffer Descriptor Field Descriptions Field Description RX Buffer Descriptor Field Descriptions Field Description RX Cppi Mode Explanation Cppi Boundary Diagram TX Buffer Descriptor Fields TX Buffer Descriptor Field Definitions Uses this bit to reclaim buffers Ssize Name Bit Access Reset Value Description TXQUEUECNTL0- Address Offset 0x7E0TXQUEUECNTL1- Address Offset 0x7E4 TXQUEUECNTL2- Address Offset 0x7E8 TXQueueMap10 2316 0x0A Detailed Data Path Description RX Operation Message Passing Software RequirementsTX Operation Queue Mapping Initialization ExampleRX Buffer Descriptor TX Buffer Descriptor NDP Maintenance Start Message Passing Doorbell Doorbell Operation Congestion Control Detailed Description Name Bit Transmit Source Flow Control Masks Configuration Bus Example Endianness Reset DMA Example Enable and Enable Status Registers Reset SummaryBLK8ENSTA BLK7ENSTA Enable and Enable Status Bit Field Descriptions EnstatGblen BLK0EN BLK1EN BLK1ENSTATBLK2EN BLK2ENSTAT Software Shutdown Details EmulationBLK8ENSTAT Peren Soft Free Enabling the Srio Peripherals Emulation Control SignalsPeren Peripheral Initializations 11.2 PLL, Ports, Device ID and Data Rate InitializationsSet Device ID Registers Assert the Peren bit to enable logical layer data flow Read register to check portx1-4 OK bit Bootload Capability ConfigurationBootload Data Movement Device Wakeup MSG REQ ERR CPU Interrupts General Description Interrupt Condition Control Registers Interrupt Source Configuration Options Where ICS0 Doorbell1, bit 0, through ICS15 Doorbell1, bit Interrupt Conditions LSU Interrupt Condition Clear Registers Iccr Address Offset ICS11 ICS10 ICS9 ICS8 ICS2 ICS1 ICS0ICC11 ICC10 ICC9 ICC8 ICC2 ICC1 ICC0 Interrupt Condition Routing Options DOORBELL0ICRR2 Address Offset LSUICRR2 Address Offset 0x02E8 LSUICRR1 Address Offset 0x02E4LSUICRR3 Address Offset 0x02EC Interrupt Status Decode Registers ERRRSTEVNTICRR2 Address Offset 0x02F4ERRRSTEVNTICRR3 Address Offset 0x02F8 ICR2 ICR1 ICR0 Sharing of Isdr Bits Interrupt Pacing Interrupt GenerationISDR3 ISDR2 ISDR1 ISDR9 ISDR8 ISDR7 ISDR6 ISDR5 ISDR4 ISDR0 Interrupt Handling INTDSTnRATECNTL Interrupt Rate Control Register Interrupt Conditions Serial Rapid IO Srio Registers IntroductionOffset Acronym Register Description Serial Rapid IO Srio Registers Offset Acronym Register Description LSUICRR3 ErrrstevnticRR2 RR3 LSU3REG1 QUEUE1TXDMAC QUEUE2TXDMACQUEUE3TXDMAC QUEUE4TXDMAC QUEUE12RXDMA Txcppiflowma SKS6SKS7 Rxqueuetear RXUMAPL18 RXUMAPH18RXUMAPL19 RXUMAPH19 Asblyid AsblyinfoPefeat Srcop SP0ERRATTRCA PTDBG0SP0ERRCAPTDB SP0ERRRATE Timer SP3ERRRATESP3ERRTHRESH Spipdiscovery Peripheral Identification Register PID Peripheral ID Register PID Field DescriptionsType Class REV Peripheral Control Register PCR Peripheral Control Register PCR Field DescriptionsPere Soft Free Bit Field Peripheral Settings Control Register Persetcntl Cbatranspr 1XMODEPrescalerse Lect ENPLL2 ENPLL3ENPLL1 Peripheral Global Enable Register Gblen Peripheral Global Enable Register Gblen Field Descriptions Peripheral Global Enable Status Register Gblenstat GBLENS TAT Block n Enable Register BLKnEN Block n Enable Register BLKnEN Field Descriptions Block n Enable Status Register BLKnENSTAT Block n Enable Status Register BLKnENSTAT RapidIO DEVICEID1 Register DEVICEIDREG1 RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions8BNODEID 16BNODEID RapidIO DEVICEID2 Register DEVICEIDREG2 RapidIO DEVICEID2 Register DEVICEIDREG2 Field Descriptions Packet Forwarding Register n for 16b DeviceIDs PF16BCNTLn Packet Forwarding Register n for 8b DeviceIDs PF8BCNTLn CDR LOS Align Term Invpa Rate Buswidth CFGRX2219 Low Freq Gain Zero Freq at e28 min Swing Invpa Rate Buswidth EnftEntx Swing Bits DE BitsCFGTX119 Amplitude mV dfpp CFGTX1512 Amplitude Reduction Serdes Macro Configuration Register n SERDESCFGnCNTL MPY EnpllRIOCLK/RIOCLK MPY DOORBELLn Interrupt Status Register DOORBELLnICSR DOORBELLn Interrupt Status Register DOORBELLnICSR DOORBELLn Interrupt Clear Register DOORBELLnICCR DOORBELLn Interrupt Clear Register DOORBELLnICCR RX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Clear Register Rxcppiiccr RX Cppi Interrupt Clear Register Rxcppiiccr TX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Clear Register Txcppiiccr TX Cppi Interrupt Clear Register Txcppiiccr LSU Status Interrupt Register Lsuicsr Field Descriptions LSU Status Interrupt Register LsuicsrICS31-0 Load/Store module interrupt condition status bits LSU Clear Interrupt Register LSU Iccr Field Descriptions LSU Clear Interrupt Register LSU IccrICS31-0 Load/Store module interrupt clear bits 31-17 126 DOORBELLn Interrupt Condition Routing Register DOORBELLnICRR 128 RX Cppi Interrupt Condition Routing Register Rxcppi Icrr ICR RX Cppi Interrupt condition routing bits RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2 RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2 TX Cppi Interrupt Condition Routing Register Txcppi Icrr ICR TX Cppi Interrupt condition routing bits TX Cppi Interrupt Condition Routing Register Txcppi ICRR2 TX Cppi Interrupt Condition Routing Register Txcppi ICRR2 LSU Module Interrupt Condition Routing Register 0 LSUICRR0 ICR LSU Module Interrupt Condition Routing Register 1 LSUICRR1 LSU Module Interrupt Condition Routing Register 1 LSUICRR1 LSU Module Interrupt Condition Routing Register 2 LSUICRR2 LSU Module Interrupt Condition Routing Register 2 LSUICRR2 LSU Module Interrupt Condition Routing Register 3 LSUICRR3 LSU Module Interrupt Condition Routing Register 3 LSUICRR3 Errrstevnticrr Errrstevnticrr Field Descriptions ERRRSTEVNTICRR2 Field Descriptions ICR11 ERRRSTEVNTICRR3 ERRRSTEVNTICRR3 Field Descriptions INTDSTn Interrupt Status Decode Registers INTDSTnDECODE INTDSTn Interrupt Status Decode Registers INTDSTnDECODE INTDSTn Interrupt Rate Control Registers INTDSTnRATECNTL CountdownvalueCountdown Value LSUn Control Register 0 LSUnREG0 LSU n Control Register 0 LSU nREG0 Field DescriptionsAddressmsb Bit Ext address fields Addresslsbconfigoffset Addresslsb Configoffse TLSUn Control Register 1 LSUnREG1 LSU n Control Register 1 LSU nREG1 Field Descriptions LSUn Control Register 2 LSUnREG2 LSU n Control Register 2 LSU nREG2 Field DescriptionsDspaddress 32b DSP byte address LSU n Control Register 3 LSU nREG3 Field Descriptions LSUn Control Register 3 LSUnREG3Bytecount LSUn Control Register 4 LSUnREG4 LSUn Control Register 4 LSUnREG4 Field Descriptions LSUn Control Register 5 LSUnREG5 LSU n Control Register 5 LSU nREG5 Field DescriptionsDrbllinfo Hopcount Packettype LSUn Control Register 6 LSUnREG6 LSUn Control Register 6 LSUnREG6 Field DescriptionsCompletioncode BSY Completionc LSU Congestion Control Flow Mask n Lsuflowmasks n Flowmask Txhdp Txcp Rxhdp Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP Transmit Queue Teardown Register Txqueueteardown QUEUE1FLOWMASK QUEUE0FLOWMASK QUEUE3FLOWMASK QUEUE2FLOWMASKQUEUE5FLOWMASK QUEUE4FLOWMASK QUEUE7FLOWMASK QUEUE6FLOWMASK QUEUE15FLOWMASK QUEUE14FLOWMASK Mask Receive Queue Teardown Register Rxqueueteardown Receive Queue Teardown Register Rxqueueteardown Receive Cppi Control Register Rxcppicntl Receive Cppi Control Register Rxcppicntl Field Descriptions Txqueuemap 3NUMMSGS3QUEUEPTR 2NUMMSGS 7NUMMSGS 7QUEUEPTR6NUMMSGS 6QUEUEPTR 11NUMMSGS 11QUEUEPTR10NUMMSGS 10QUEUEPTR 15NUMMSGS 15QUEUEPTR14NUMMSGS 14QUEUEPTR Mailbox-to-Queue Mapping Register Ln RXUMAPLn Mailbox-to-Queue Mapping Register Hn RXUMAPHn Flow Control Table Entry Registers FLOWCNTLn Flowcntlid Device Identity CAR Devid Device Identity CAR Devid Field Descriptions Device Information CAR Devinfo Device Information CAR Devinfo Field DescriptionsDevicerev Vendor supply device revision Assembly Identity CAR Asblyid Assembly Identity CAR Asblyid Field Descriptions Assembly Information CAR Asblyinfo Assembly Information CAR Asblyinfo Field Descriptions Processing Element Features CAR Pefeat Processing Element Features CAR Pefeat Field Descriptions Source Operations CAR Srcop Source Operations CAR Srcop Field Descriptions Destination Operations CAR Destop Destination Operations CAR Destop Field Descriptions Processing Element Logical Layer Control CSR Pellctl ExtendedaddressIngcontrol Ressingcont Local Configuration Space Base Address 0 CSR Lclcfghbar Lcsba Local Configuration Space Base Address 1 CSR Lclcfgbar Local Configuration Space Base Address 1 CSR Lclcfgbar Base Device ID CSR Baseid Base Device ID CSR Baseid Field Descriptions Host Base Device ID Lock CSR Hostbaseidlock HostbasedeviceidHostbasede Viceid Component Tag CSR Comptag Field Descriptions Component Tag CSR ComptagComponenttag Efptr Efid Port Link Timeout Control CSR Spltctl Field Descriptions Port Link Time-Out Control CSR Spltctl Port Response Time-Out Control CSR Sprtctl Port Response Time-Out Control CSR Sprtctl Port General Control CSR Spgenctl Port General Control CSR Spgenctl Field Descriptions Port Link Maintenance Request CSR n SPnLMREQ Command Port Link Maintenance Response CSR n SPnLMRESP Port Local AckID Status CSR n SPnACKIDSTAT Port Error and Status CSR n SPnERRSTAT Port Error and Status CSR n SPnERRSTAT Field Descriptions Portuninitia PortokLized Port Control CSR n SPnCTL Port Control CSR n SPnCTL Field Descriptions Port Control CSR n SP nCTL Field Descriptions Nable Error Reporting Block Header Errrptbh Error Reporting Block Header Errrptbh Field Descriptions Logical/Transport Layer Error Detect CSR Errdet Logical/Transport Layer Error Enable CSR Erren ADDRESS6332 Logical/Transport Layer High Address Capture CSR Haddrcapt50 bit addresses ADDRESS313 Logical/Transport Layer Address Capture CSR AddrcaptXamsbs Logical/Transport Layer Device ID Capture CSR Idcapt Msbdestid DestidMsbsourceid Sourceid Msbdestid Logical/Transport Layer Control Capture CSR Ctrlcapt Ftype Ttype MsginfoImpspecific Ftype Port-Write Target Device ID CSR Pwtgtid Port-Write Target Device ID CSR Pwtgtid Field DescriptionsDeviceidmsb Deviceid Port Error Detect CSR n SPnERRDET Port Error Detect CSR n SPnERRDET Field Descriptions Port Error Rate Enable CSR n SPnRATEEN Port Error Rate Enable CSR n SPnRATEEN Field Descriptions Port n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0 CAPTURE0 CAPTURE0 CAPTURE1 CAPTURE1 CAPTURE2 CAPTURE2 CAPTURE3 CAPTURE3 Port Error Rate CSR n SPnERRRATE Port Error Rate CSR n SPnERRRATE Field Descriptions Port Error Rate Threshold CSR n SPnERRTHRESH Port IP Discovery Timer in 4x mode Spipdiscoverytimer DiscoverytimerPwtimer Discoveryti Port IP Mode CSR Spipmode Port IP Mode CSR Spipmode Field Descriptions Port IP Mode CSR Spipmode Field Descriptions Rsten Serial Port IP Prescalar Ipprescal Field Descriptions Serial Port IP Prescalar IpprescalPrescale Port-Write-In Capture CSR n SPIPPWINCAPTn Pwcapt Port Reset Option CSR n SP nRSTOPT Field Descriptions Port Reset Option CSR n SPnRSTOPTPortid Port Control Independent Register n SPnCTLINDEP Maxretryen MaxretryerMaxretryth Irqen Port Silence Timer n SPnSILENCETIMER Field Descriptions Port Silence Timer n SPnSILENCETIMERSilencetimer Multevntcs Multevntcs Port Control Symbol Transmit n SPnCSTX Port Control Symbol Transmit n SP nCSTX Field Descriptions Important Notice