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Texas Instruments TMS320C645x Processing Element Logical Layer Control CSR Pellctl, Ingcontrol

Models: TMS320C645x

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SRIO Registers

5.71Processing Element Logical Layer Control CSR (PE_LL_CTL)

Figure 127. Processing Element Logical Layer Control CSR (PE_LL_CTL)

	31-16
	Reserved
	R-0x0000
LEGEND: R = Read only; -n= value after reset
15-3	2-0
Reserved	EXTENDED_ADDRESS
	ING_CONTROL
R-0x0000	RW-0x0001
LEGEND: R = Read only; -n= value after reset

Table 101. Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions

Bit	Field	Value	Description
31-3	Reserved		Reserved
2-0	EXTENDED_ADD		Controls the number of address bits generated by the PE as a source and processed by the PE as
	RESSING_CONT		the target of an operation. All other encodings reserved.
	ROL	100b	PE supports 66 bit addresses
		100b	PE supports 66 bit addresses
		010b	PE supports 50 bit addresses
		001b	PE supports 34 bit addresses

SPRU976 –March 2006

Serial RapidIO (SRIO)

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Texas Instruments TMS320C645x manual Processing Element Logical Layer Control CSR Pellctl, Extendedaddress, Ingcontrol, Rol

Contents

Users Guide Submit Documentation Feedback Contents Errrstevnticrr Base Device ID CSR Baseid List of Figures Load/Store Module Interrupt Condition Routing Registers 150 Port Error Rate Threshold CSR n SP n Errthresh List of Tables LSUn Control Register 0 LSUnREG0 Field Descriptions Base Device ID CSR Baseid Field Descriptions Read This First RapidIO Architectural Hierarchy General RapidIO SystemOverview 3 1x/4x LP-Serial RapidIO Interconnect ArchitectureFeatures Supported in Srio RapidIO Feature Support in SrioStandards Features Not SupportedExternal Devices Requirements RapidIO Documents and LinksPeripheral Data Flow OverviewOperation Sequence Srio PacketsExample Packet Streaming Write Operation Sequence4x RapidIO Packet Data Stream Streaming-Write Class Control SymbolsFtype Ttype Packet Type Srio Packet Ftype/TtypePacket Type Block Diagram Srio PinsFunctional Operation Pin DescriptionSrio Conceptual Block Diagram Enabling the PLL Serdes and its ConfigurationsBits of Serdescfg nCNTL Register 0x120 0x12c Bit Name Value DescriptionRate Bit Effects Bits of Serdescfg nCNTL Register 0x120 0x12cLine Rate versus PLL Output Clock Frequency Bits of Serdescfgrx nCNTL Registers Frequency Range versus MPYEnabling the Receiver Bit Field Value Description 1514 Disabled. Loss of signal detection disabledBits of SERDESCFGRXnCNTL Registers Enabling the Transmitter EQ BitsBits of Serdescfgtx nCNTL Registers CFGRX2219 Low Freq GainDE Bits Bits of Serdescfgtx nCNTL RegistersSwing Bits DirectIO Serdes Configuration ExampleRapidIO Packet Header Field Control/Command Register Field MappingStatus Fields Control/Command Register RapidIO Packet Header FieldStatus Field Function BSYLSU Registers Timing Detailed Data Path Description Example Burst NwriterWrite Transactions TX OperationRead Transactions RX Operation SegmentationMessage Passing Reset and Power Down StateCppi RX Scheme for RapidIO Queue Mapping Table Address Offset 0x0800 0x08FC Bit Name Description Queue Mapping Register Rxumapl nRX Buffer Descriptor Fields Field Description RX Buffer Descriptor Field DescriptionsField Description RX Buffer Descriptor Field DescriptionsRX Cppi Mode Explanation Cppi Boundary Diagram TX Buffer Descriptor Field Definitions TX Buffer Descriptor FieldsUses this bit to reclaim buffers Ssize TXQUEUECNTL0- Address Offset 0x7E0 Name Bit Access Reset Value DescriptionTXQUEUECNTL1- Address Offset 0x7E4 TXQUEUECNTL2- Address Offset 0x7E8TXQueueMap10 2316 0x0A Detailed Data Path Description TX Operation Message Passing Software RequirementsRX Operation RX Buffer Descriptor Initialization ExampleQueue Mapping NDP TX Buffer DescriptorStart Message Passing MaintenanceDoorbell Operation DoorbellDetailed Description Congestion ControlName Bit Transmit Source Flow Control Masks Endianness Configuration Bus ExampleDMA Example ResetBLK8ENSTA BLK7ENSTA Reset SummaryEnable and Enable Status Registers Enstat Enable and Enable Status Bit Field DescriptionsGblen BLK0ENBLK1ENSTAT BLK1ENBLK2EN BLK2ENSTATEmulation Software Shutdown DetailsBLK8ENSTAT Peren Soft FreePeren Emulation Control SignalsEnabling the Srio Peripherals Set Device ID Registers 11.2 PLL, Ports, Device ID and Data Rate InitializationsPeripheral Initializations Read register to check portx1-4 OK bit Assert the Peren bit to enable logical layer data flowConfiguration Bootload CapabilityBootload Data Movement Device WakeupERR MSG REQGeneral Description CPU InterruptsInterrupt Condition Control Registers Interrupt Source Configuration Options Where ICS0 Doorbell1, bit 0, through ICS15 Doorbell1, bit Interrupt Conditions LSU Interrupt Condition Clear Registers Iccr Address Offset ICS2 ICS1 ICS0 ICS11 ICS10 ICS9 ICS8ICC11 ICC10 ICC9 ICC8 ICC2 ICC1 ICC0DOORBELL0ICRR2 Address Offset Interrupt Condition Routing OptionsLSUICRR3 Address Offset 0x02EC LSUICRR1 Address Offset 0x02E4LSUICRR2 Address Offset 0x02E8 ERRRSTEVNTICRR2 Address Offset 0x02F4 Interrupt Status Decode RegistersERRRSTEVNTICRR3 Address Offset 0x02F8 ICR2 ICR1 ICR0Sharing of Isdr Bits ISDR3 ISDR2 ISDR1 ISDR9 ISDR8 ISDR7 ISDR6 ISDR5 ISDR4 ISDR0 Interrupt GenerationInterrupt Pacing INTDSTnRATECNTL Interrupt Rate Control Register Interrupt HandlingInterrupt Conditions Offset Acronym Register Description IntroductionSerial Rapid IO Srio Registers Offset Acronym Register Description Serial Rapid IO Srio RegistersErrrstevntic LSUICRR3RR2 RR3LSU3REG1 QUEUE2TXDMAC QUEUE1TXDMACQUEUE3TXDMAC QUEUE4TXDMACQUEUE12RXDMA SKS6 TxcppiflowmaSKS7 RxqueuetearRXUMAPH18 RXUMAPL18RXUMAPL19 RXUMAPH19Asblyinfo AsblyidPefeat SrcopPTDBG0 SP0ERRATTRCASP0ERRCAPTDB SP0ERRRATESP3ERRRATE TimerSP3ERRTHRESH SpipdiscoveryPeripheral ID Register PID Field Descriptions Peripheral Identification Register PIDType Class REVPeripheral Control Register PCR Field Descriptions Peripheral Control Register PCRPere Soft Free Bit FieldPeripheral Settings Control Register Persetcntl 1XMODE CbatransprPrescalerse LectENPLL1 ENPLL3ENPLL2 Peripheral Global Enable Register Gblen Field Descriptions Peripheral Global Enable Register GblenGBL Peripheral Global Enable Status Register GblenstatENS TATBlock n Enable Register BLKnEN Field Descriptions Block n Enable Register BLKnENBlock n Enable Status Register BLKnENSTAT Block n Enable Status Register BLKnENSTATRapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions RapidIO DEVICEID1 Register DEVICEIDREG18BNODEID 16BNODEIDRapidIO DEVICEID2 Register DEVICEIDREG2 Field Descriptions RapidIO DEVICEID2 Register DEVICEIDREG2Packet Forwarding Register n for 16b DeviceIDs PF16BCNTLn Packet Forwarding Register n for 8b DeviceIDs PF8BCNTLn Term Invpa Rate Buswidth CDR LOS AlignCFGRX2219 Low Freq Gain Zero Freq at e28 min Entx EnftSwing Invpa Rate Buswidth DE Bits Swing BitsCFGTX119 Amplitude mV dfpp CFGTX1512 Amplitude ReductionMPY Enpll Serdes Macro Configuration Register n SERDESCFGnCNTLRIOCLK/RIOCLK MPYDOORBELLn Interrupt Status Register DOORBELLnICSR DOORBELLn Interrupt Status Register DOORBELLnICSRDOORBELLn Interrupt Clear Register DOORBELLnICCR DOORBELLn Interrupt Clear Register DOORBELLnICCRRX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Status Register RxcppiicsrRX Cppi Interrupt Clear Register Rxcppiiccr RX Cppi Interrupt Clear Register RxcppiiccrTX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Status Register TxcppiicsrTX Cppi Interrupt Clear Register Txcppiiccr TX Cppi Interrupt Clear Register TxcppiiccrICS31-0 Load/Store module interrupt condition status bits LSU Status Interrupt Register LsuicsrLSU Status Interrupt Register Lsuicsr Field Descriptions ICS31-0 Load/Store module interrupt clear bits LSU Clear Interrupt Register LSU IccrLSU Clear Interrupt Register LSU Iccr Field Descriptions 31-17 126 DOORBELLn Interrupt Condition Routing Register DOORBELLnICRR 128 ICR RX Cppi Interrupt condition routing bits RX Cppi Interrupt Condition Routing Register Rxcppi IcrrRX Cppi Interrupt Condition Routing Register Rxcppi ICRR2 RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2ICR TX Cppi Interrupt condition routing bits TX Cppi Interrupt Condition Routing Register Txcppi IcrrTX Cppi Interrupt Condition Routing Register Txcppi ICRR2 TX Cppi Interrupt Condition Routing Register Txcppi ICRR2ICR LSU Module Interrupt Condition Routing Register 0 LSUICRR0LSU Module Interrupt Condition Routing Register 1 LSUICRR1 LSU Module Interrupt Condition Routing Register 1 LSUICRR1LSU Module Interrupt Condition Routing Register 2 LSUICRR2 LSU Module Interrupt Condition Routing Register 2 LSUICRR2LSU Module Interrupt Condition Routing Register 3 LSUICRR3 LSU Module Interrupt Condition Routing Register 3 LSUICRR3Errrstevnticrr Field Descriptions ErrrstevnticrrICR11 ERRRSTEVNTICRR2 Field DescriptionsERRRSTEVNTICRR3 Field Descriptions ERRRSTEVNTICRR3INTDSTn Interrupt Status Decode Registers INTDSTnDECODE INTDSTn Interrupt Status Decode Registers INTDSTnDECODECountdownvalue INTDSTn Interrupt Rate Control Registers INTDSTnRATECNTLCountdown ValueLSU n Control Register 0 LSU nREG0 Field Descriptions LSUn Control Register 0 LSUnREG0Addressmsb Bit Ext address fieldsAddresslsb Configoffse T AddresslsbconfigoffsetLSUn Control Register 1 LSUnREG1 LSU n Control Register 1 LSU nREG1 Field DescriptionsLSU n Control Register 2 LSU nREG2 Field Descriptions LSUn Control Register 2 LSUnREG2Dspaddress 32b DSP byte addressBytecount LSUn Control Register 3 LSUnREG3LSU n Control Register 3 LSU nREG3 Field Descriptions LSUn Control Register 4 LSUnREG4 Field Descriptions LSUn Control Register 4 LSUnREG4LSU n Control Register 5 LSU nREG5 Field Descriptions LSUn Control Register 5 LSUnREG5Drbllinfo Hopcount PackettypeLSUn Control Register 6 LSUnREG6 Field Descriptions LSUn Control Register 6 LSUnREG6Completioncode BSY CompletioncFlowmask LSU Congestion Control Flow Mask n Lsuflowmasks nTxhdp Txcp Rxhdp Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACPTransmit Queue Teardown Register Txqueueteardown QUEUE3FLOWMASK QUEUE2FLOWMASK QUEUE1FLOWMASK QUEUE0FLOWMASKQUEUE5FLOWMASK QUEUE4FLOWMASK QUEUE7FLOWMASK QUEUE6FLOWMASKMask QUEUE15FLOWMASK QUEUE14FLOWMASKReceive Queue Teardown Register Rxqueueteardown Receive Queue Teardown Register RxqueueteardownReceive Cppi Control Register Rxcppicntl Field Descriptions Receive Cppi Control Register Rxcppicntl3NUMMSGS Txqueuemap3QUEUEPTR 2NUMMSGS7QUEUEPTR 7NUMMSGS6NUMMSGS 6QUEUEPTR11QUEUEPTR 11NUMMSGS10NUMMSGS 10QUEUEPTR15QUEUEPTR 15NUMMSGS14NUMMSGS 14QUEUEPTRMailbox-to-Queue Mapping Register Ln RXUMAPLn Mailbox-to-Queue Mapping Register Hn RXUMAPHn Flowcntlid Flow Control Table Entry Registers FLOWCNTLnDevice Identity CAR Devid Field Descriptions Device Identity CAR DevidDevice Information CAR Devinfo Field Descriptions Device Information CAR DevinfoDevicerev Vendor supply device revisionAssembly Identity CAR Asblyid Field Descriptions Assembly Identity CAR AsblyidAssembly Information CAR Asblyinfo Field Descriptions Assembly Information CAR AsblyinfoProcessing Element Features CAR Pefeat Field Descriptions Processing Element Features CAR PefeatSource Operations CAR Srcop Field Descriptions Source Operations CAR SrcopDestination Operations CAR Destop Field Descriptions Destination Operations CAR DestopExtendedaddress Processing Element Logical Layer Control CSR PellctlIngcontrol RessingcontLcsba Local Configuration Space Base Address 0 CSR LclcfghbarLocal Configuration Space Base Address 1 CSR Lclcfgbar Local Configuration Space Base Address 1 CSR LclcfgbarBase Device ID CSR Baseid Field Descriptions Base Device ID CSR BaseidHostbasedeviceid Host Base Device ID Lock CSR HostbaseidlockHostbasede ViceidComponenttag Component Tag CSR ComptagComponent Tag CSR Comptag Field Descriptions Efid EfptrPort Link Time-Out Control CSR Spltctl Port Link Timeout Control CSR Spltctl Field DescriptionsPort Response Time-Out Control CSR Sprtctl Port Response Time-Out Control CSR SprtctlPort General Control CSR Spgenctl Field Descriptions Port General Control CSR SpgenctlCommand Port Link Maintenance Request CSR n SPnLMREQPort Link Maintenance Response CSR n SPnLMRESP Port Local AckID Status CSR n SPnACKIDSTAT Port Error and Status CSR n SPnERRSTAT Field Descriptions Port Error and Status CSR n SPnERRSTATLized PortokPortuninitia Port Control CSR n SPnCTL Field Descriptions Port Control CSR n SPnCTLNable Port Control CSR n SP nCTL Field DescriptionsError Reporting Block Header Errrptbh Field Descriptions Error Reporting Block Header ErrrptbhLogical/Transport Layer Error Detect CSR Errdet Logical/Transport Layer Error Enable CSR Erren 50 bit addresses Logical/Transport Layer High Address Capture CSR HaddrcaptADDRESS6332 Xamsbs Logical/Transport Layer Address Capture CSR AddrcaptADDRESS313 Msbdestid Destid Logical/Transport Layer Device ID Capture CSR IdcaptMsbsourceid Sourceid MsbdestidFtype Ttype Msginfo Logical/Transport Layer Control Capture CSR CtrlcaptImpspecific FtypePort-Write Target Device ID CSR Pwtgtid Field Descriptions Port-Write Target Device ID CSR PwtgtidDeviceidmsb DeviceidPort Error Detect CSR n SPnERRDET Field Descriptions Port Error Detect CSR n SPnERRDETPort Error Rate Enable CSR n SPnRATEEN Field Descriptions Port Error Rate Enable CSR n SPnRATEENPort n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0 CAPTURE0 CAPTURE0CAPTURE1 CAPTURE1CAPTURE2 CAPTURE2CAPTURE3 CAPTURE3Port Error Rate CSR n SPnERRRATE Field Descriptions Port Error Rate CSR n SPnERRRATEPort Error Rate Threshold CSR n SPnERRTHRESH Discoverytimer Port IP Discovery Timer in 4x mode SpipdiscoverytimerPwtimer DiscoverytiPort IP Mode CSR Spipmode Field Descriptions Port IP Mode CSR SpipmodeRsten Port IP Mode CSR Spipmode Field DescriptionsPrescale Serial Port IP Prescalar IpprescalSerial Port IP Prescalar Ipprescal Field Descriptions Pwcapt Port-Write-In Capture CSR n SPIPPWINCAPTnPortid Port Reset Option CSR n SPnRSTOPTPort Reset Option CSR n SP nRSTOPT Field Descriptions Port Control Independent Register n SPnCTLINDEP Maxretryer MaxretryenMaxretryth IrqenSilencetimer Port Silence Timer n SPnSILENCETIMERPort Silence Timer n SPnSILENCETIMER Field Descriptions Multevntcs MultevntcsPort Control Symbol Transmit n SP nCSTX Field Descriptions Port Control Symbol Transmit n SPnCSTXImportant Notice