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SRIO Registers
5.71Processing Element Logical Layer Control CSR (PE_LL_CTL)
Figure 127. Processing Element Logical Layer Control CSR (PE_LL_CTL)
| |
| Reserved |
| |
LEGEND: R = Read only; |
|
Reserved | EXTENDED_ADDRESS |
| ING_CONTROL |
LEGEND: R = Read only; |
|
Table 101. Processing Element Logical Layer Control CSR (PE_LL_CTL) Field Descriptions
Bit | Field | Value | Description |
Reserved |
| Reserved | |
EXTENDED_ADD |
| Controls the number of address bits generated by the PE as a source and processed by the PE as | |
| RESSING_CONT |
| the target of an operation. All other encodings reserved. |
| ROL | 100b | PE supports 66 bit addresses |
|
| ||
|
| 010b | PE supports 50 bit addresses |
|
| 001b | PE supports 34 bit addresses |
SPRU976 | Serial RapidIO (SRIO) | 173 |