Texas Instruments TMS320C645x manual Read register to check portx1-4 OK bit

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SRIO Functional Description

}

else{

SRIO_REGS->SP_IP_MODE = 0x04000000; // Jadis mltc/rst/pw enable, clear

}
SRIO_REGS->IP_PRESCAL	= 0x00000021;	// srv_clk prescalar=0x21 (333MHz)
SRIO_REGS->SP0_SILENCE_TIMER = 0x20000000;		// 0, short cycles for sim
SRIO_REGS->SP1_SILENCE_TIMER = 0x20000000;		// 0, short cycles for sim
SRIO_REGS->SP2_SILENCE_TIMER = 0x20000000;		// 0, short cycles for sim
SRIO_REGS->SP3_SILENCE_TIMER = 0x20000000;		// 0, short cycles for sim
SRIO_REGS->PER_SET_CNTL	= 0x01000000;	// bootcmpl=1
SRIO_REGS->SP_LT_CTL	= 0xFFFFFF00;	// long
SRIO_REGS->SP_RT_CTL	= 0xFFFFFF00;	// long
SRIO_REGS->SP_GEN_CTL	= 0x40000000;	// agent, master, undiscovered
SRIO_REGS->SP0_CTL	= 0x00600000;	// enable i/o
SRIO_REGS->SP1_CTL	= 0x00600000;	// enable i/o
SRIO_REGS->SP2_CTL	= 0x00600000;	// enable i/o
SRIO_REGS->SP3_CTL	= 0x00600000;	// enable i/o
SRIO_REGS->ERR_RPT_BH	= 0x00000000;	// next ext=0x0000(last)

SRIO_REGS->ERR_DET SRIO_REGS->ERR_EN SRIO_REGS->H_ADDR_CAPT SRIO_REGS->ADDR_CAPT SRIO_REGS->ID_CAPT SRIO_REGS->CTRL_CAPT

=0x00000000 ; // clear

=0x00000000 ; // disable

=0x00000000 ; // clear

=0x00000000 ; // clear

=0x00000000 ; // clear

=0x00000000 ; // clear

SRIO_REGS->SP_IP_MODE = 0x0000003F; // mltc/rst/pw enable, clear

SRIO_REGS->SP_IP_PW_IN_CAPT0 = 0x00000000 ; // clear

SRIO_REGS->SP_IP_PW_IN_CAPT1 = 0x00000000 ; // clear

SRIO_REGS->SP_IP_PW_IN_CAPT2 = 0x00000000 ; // clear

SRIO_REGS->SP_IP_PW_IN_CAPT3 = 0x00000000 ; // clear

//INIT_WAIT wait for lane initialization

Read register to check portx(1-4) OK bit

//polling SRIO_MAC's port_ok bit rdata = SRIO_REGS->P0_ERR_STAT ;

while ((rdata & 0x00000002) != 0x00000002)

{

rdata = SRIO_REGS->P0_ERR_STAT ;

}

if (srio4p1x_mode){

rdata = SRIO_REGS->P1_ERR_STAT;

while ((rdata & 0x00000002) != 0x00000002)

{

rdata = SRIO_REGS->P1_ERR_STAT;

}

rdata = SRIO_REGS->P2_ERR_STAT;

while ((rdata & 0x00000002) != 0x00000002)

{

rdata = SRIO_REGS->P2_ERR_STAT;

}

rdata = SRIO_REGS->P3_ERR_STAT;

while ((rdata & 0x00000002) != 0x00000002)

{

rdata = SRIO_REGS->P3_ERR_STAT;

}

}

Assert the PEREN bit to enable logical layer data flow

SRIO_REGS->PCR = 0x00000004;	// peren
SPRU976 –March 2006	Serial RapidIO (SRIO)	71

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