Cppi RX Scheme for RapidIO | Texas Instruments TMS320C645x instruction

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SRIO Functional Description

2.3.4.1RX Operation

As message packets are received by the RapidIO ports, the data must be written into memory while maintaining accurate state information that is needed for future processing. For instance, if a message spans multiple packets, information must be saved that allows re-assembly of those packets by the CPU. The CPPI module provides a scheme for tracking single and multi-packet messages, linking messages in queues, and generating interrupts. Figure 14 illustrates the scheme.

Figure 14. CPPI RX Scheme for RapidIO

Mailbox from

Header

input

Mailbox


Q15		Q2	Q1	Q0

Queue

Packet

Manager

nA

n+1 B

n+2 B

n+3 C

n+4 D

n+5 B

n+6	E
	Message
Packet

Buffer

Queues:

Descriptor

All

Dedicated
Message
	L2
A	Data	fer
C	n
	n+3
D	n+4
	n+4
E	n+6
null	256B	fer
	L2
	Data	fer
	n+1
	n+2
	n+5

Multi-Segment

Descriptor

B

Multi-Segment

Descriptor

null

4KB

fer

Messages addressed to any of the 64 mailbox locations can be received on any of the RapidIO ports simultaneously. Packets are handled sequentially in order of receipt. The function of the mailbox mapper block is to direct the inbound messages to the appropriate queue and finally to the correct core. The queue mapping is programmable and must be configured after device reset. RapidIO originally supported only 4 mailboxes with 4 letters/mailbox. Letters allow concurrent message traffic between sender and receiver. However, for messages that consist of only single packets, the unused 4-bit packet field normally indicating the message segment extends the available number of mailboxes. Figure 15 shows the packet header fields for message requests.

Figure 15. Message Request Packet

n*64+64

PHY	TRA	LOG	TRA	LOG	PHY
10	2	4	16	n*64+16	16

acklD	rsv	prio	tt	ftype	destID sourcelD		msglen	ssize	letter	mbox	msgseg/xmbox double-word		double-word	...	double-word	double-word	CRC
5	3	2	2	4	8	8	4	4	2	2	4	64	64	(n-4)*64	64	64	16
ftype	1

SPRU976 –March 2006

Serial RapidIO (SRIO)

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Texas Instruments TMS320C645x manual Cppi RX Scheme for RapidIO

Contents

Users Guide Submit Documentation Feedback Contents Errrstevnticrr Base Device ID CSR Baseid List of Figures Load/Store Module Interrupt Condition Routing Registers 150 Port Error Rate Threshold CSR n SP n Errthresh List of Tables LSUn Control Register 0 LSUnREG0 Field Descriptions Base Device ID CSR Baseid Field Descriptions Read This First RapidIO Architectural Hierarchy General RapidIO System Overview 3 1x/4x LP-Serial RapidIO Interconnect Architecture Features Supported in Srio RapidIO Feature Support in Srio Standards Features Not SupportedExternal Devices Requirements RapidIO Documents and Links Peripheral Data Flow Overview Operation Sequence Srio Packets Example Packet Streaming Write Operation Sequence 4x RapidIO Packet Data Stream Streaming-Write Class Control Symbols Ftype Ttype Packet Type Srio Packet Ftype/TtypePacket Type Block Diagram Srio PinsFunctional Operation Pin Description Srio Conceptual Block Diagram Enabling the PLL Serdes and its ConfigurationsBits of Serdescfg nCNTL Register 0x120 0x12c Bit Name Value Description Rate Bit Effects Bits of Serdescfg nCNTL Register 0x120 0x12cLine Rate versus PLL Output Clock Frequency Bits of Serdescfgrx nCNTL Registers Frequency Range versus MPYEnabling the Receiver Bit Field Value Description 1514 Disabled. Loss of signal detection disabledBits of SERDESCFGRXnCNTL Registers Enabling the Transmitter EQ BitsBits of Serdescfgtx nCNTL Registers CFGRX2219 Low Freq Gain DE Bits Bits of Serdescfgtx nCNTL RegistersSwing Bits DirectIO Serdes Configuration Example RapidIO Packet Header Field Control/Command Register Field Mapping Status Fields Control/Command Register RapidIO Packet Header FieldStatus Field Function BSY LSU Registers Timing Detailed Data Path Description Example Burst Nwriter Write Transactions TX Operation Read Transactions RX Operation Segmentation Message Passing Reset and Power Down State Cppi RX Scheme for RapidIO Queue Mapping Table Address Offset 0x0800 0x08FC Bit Name Description Queue Mapping Register Rxumapl n RX Buffer Descriptor Fields Field Description RX Buffer Descriptor Field Descriptions Field Description RX Buffer Descriptor Field Descriptions RX Cppi Mode Explanation Cppi Boundary Diagram TX Buffer Descriptor Field Definitions TX Buffer Descriptor Fields Uses this bit to reclaim buffers Ssize TXQUEUECNTL0- Address Offset 0x7E0 Name Bit Access Reset Value DescriptionTXQUEUECNTL1- Address Offset 0x7E4 TXQUEUECNTL2- Address Offset 0x7E8 TXQueueMap10 2316 0x0A Detailed Data Path Description TX Operation Message Passing Software RequirementsRX Operation RX Buffer Descriptor Initialization ExampleQueue Mapping NDP TX Buffer Descriptor Start Message Passing Maintenance Doorbell Operation Doorbell Detailed Description Congestion Control Name Bit Transmit Source Flow Control Masks Endianness Configuration Bus Example DMA Example Reset BLK8ENSTA BLK7ENSTA Reset SummaryEnable and Enable Status Registers Enstat Enable and Enable Status Bit Field DescriptionsGblen BLK0EN BLK1ENSTAT BLK1ENBLK2EN BLK2ENSTAT Emulation Software Shutdown DetailsBLK8ENSTAT Peren Soft Free Peren Emulation Control SignalsEnabling the Srio Peripherals Set Device ID Registers 11.2 PLL, Ports, Device ID and Data Rate InitializationsPeripheral Initializations Read register to check portx1-4 OK bit Assert the Peren bit to enable logical layer data flow Configuration Bootload CapabilityBootload Data Movement Device Wakeup ERR MSG REQ General Description CPU Interrupts Interrupt Condition Control Registers Interrupt Source Configuration Options Where ICS0 Doorbell1, bit 0, through ICS15 Doorbell1, bit Interrupt Conditions LSU Interrupt Condition Clear Registers Iccr Address Offset ICS2 ICS1 ICS0 ICS11 ICS10 ICS9 ICS8ICC11 ICC10 ICC9 ICC8 ICC2 ICC1 ICC0 DOORBELL0ICRR2 Address Offset Interrupt Condition Routing Options LSUICRR3 Address Offset 0x02EC LSUICRR1 Address Offset 0x02E4LSUICRR2 Address Offset 0x02E8 ERRRSTEVNTICRR2 Address Offset 0x02F4 Interrupt Status Decode RegistersERRRSTEVNTICRR3 Address Offset 0x02F8 ICR2 ICR1 ICR0 Sharing of Isdr Bits ISDR3 ISDR2 ISDR1 ISDR9 ISDR8 ISDR7 ISDR6 ISDR5 ISDR4 ISDR0 Interrupt GenerationInterrupt Pacing INTDSTnRATECNTL Interrupt Rate Control Register Interrupt Handling Interrupt Conditions Offset Acronym Register Description IntroductionSerial Rapid IO Srio Registers Offset Acronym Register Description Serial Rapid IO Srio Registers Errrstevntic LSUICRR3RR2 RR3 LSU3REG1 QUEUE2TXDMAC QUEUE1TXDMACQUEUE3TXDMAC QUEUE4TXDMAC QUEUE12RXDMA SKS6 TxcppiflowmaSKS7 Rxqueuetear RXUMAPH18 RXUMAPL18RXUMAPL19 RXUMAPH19 Asblyinfo AsblyidPefeat Srcop PTDBG0 SP0ERRATTRCASP0ERRCAPTDB SP0ERRRATE SP3ERRRATE TimerSP3ERRTHRESH Spipdiscovery Peripheral ID Register PID Field Descriptions Peripheral Identification Register PIDType Class REV Peripheral Control Register PCR Field Descriptions Peripheral Control Register PCRPere Soft Free Bit Field Peripheral Settings Control Register Persetcntl 1XMODE CbatransprPrescalerse Lect ENPLL1 ENPLL3ENPLL2 Peripheral Global Enable Register Gblen Field Descriptions Peripheral Global Enable Register Gblen GBL Peripheral Global Enable Status Register GblenstatENS TAT Block n Enable Register BLKnEN Field Descriptions Block n Enable Register BLKnEN Block n Enable Status Register BLKnENSTAT Block n Enable Status Register BLKnENSTAT RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions RapidIO DEVICEID1 Register DEVICEIDREG18BNODEID 16BNODEID RapidIO DEVICEID2 Register DEVICEIDREG2 Field Descriptions RapidIO DEVICEID2 Register DEVICEIDREG2 Packet Forwarding Register n for 16b DeviceIDs PF16BCNTLn Packet Forwarding Register n for 8b DeviceIDs PF8BCNTLn Term Invpa Rate Buswidth CDR LOS Align CFGRX2219 Low Freq Gain Zero Freq at e28 min Entx EnftSwing Invpa Rate Buswidth DE Bits Swing BitsCFGTX119 Amplitude mV dfpp CFGTX1512 Amplitude Reduction MPY Enpll Serdes Macro Configuration Register n SERDESCFGnCNTLRIOCLK/RIOCLK MPY DOORBELLn Interrupt Status Register DOORBELLnICSR DOORBELLn Interrupt Status Register DOORBELLnICSR DOORBELLn Interrupt Clear Register DOORBELLnICCR DOORBELLn Interrupt Clear Register DOORBELLnICCR RX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Clear Register Rxcppiiccr RX Cppi Interrupt Clear Register Rxcppiiccr TX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Clear Register Txcppiiccr TX Cppi Interrupt Clear Register Txcppiiccr ICS31-0 Load/Store module interrupt condition status bits LSU Status Interrupt Register LsuicsrLSU Status Interrupt Register Lsuicsr Field Descriptions ICS31-0 Load/Store module interrupt clear bits LSU Clear Interrupt Register LSU IccrLSU Clear Interrupt Register LSU Iccr Field Descriptions 31-17 126 DOORBELLn Interrupt Condition Routing Register DOORBELLnICRR 128 ICR RX Cppi Interrupt condition routing bits RX Cppi Interrupt Condition Routing Register Rxcppi Icrr RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2 RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2 ICR TX Cppi Interrupt condition routing bits TX Cppi Interrupt Condition Routing Register Txcppi Icrr TX Cppi Interrupt Condition Routing Register Txcppi ICRR2 TX Cppi Interrupt Condition Routing Register Txcppi ICRR2 ICR LSU Module Interrupt Condition Routing Register 0 LSUICRR0 LSU Module Interrupt Condition Routing Register 1 LSUICRR1 LSU Module Interrupt Condition Routing Register 1 LSUICRR1 LSU Module Interrupt Condition Routing Register 2 LSUICRR2 LSU Module Interrupt Condition Routing Register 2 LSUICRR2 LSU Module Interrupt Condition Routing Register 3 LSUICRR3 LSU Module Interrupt Condition Routing Register 3 LSUICRR3 Errrstevnticrr Field Descriptions Errrstevnticrr ICR11 ERRRSTEVNTICRR2 Field Descriptions ERRRSTEVNTICRR3 Field Descriptions ERRRSTEVNTICRR3 INTDSTn Interrupt Status Decode Registers INTDSTnDECODE INTDSTn Interrupt Status Decode Registers INTDSTnDECODE Countdownvalue INTDSTn Interrupt Rate Control Registers INTDSTnRATECNTLCountdown Value LSU n Control Register 0 LSU nREG0 Field Descriptions LSUn Control Register 0 LSUnREG0Addressmsb Bit Ext address fields Addresslsb Configoffse T AddresslsbconfigoffsetLSUn Control Register 1 LSUnREG1 LSU n Control Register 1 LSU nREG1 Field Descriptions LSU n Control Register 2 LSU nREG2 Field Descriptions LSUn Control Register 2 LSUnREG2Dspaddress 32b DSP byte address Bytecount LSUn Control Register 3 LSUnREG3LSU n Control Register 3 LSU nREG3 Field Descriptions LSUn Control Register 4 LSUnREG4 Field Descriptions LSUn Control Register 4 LSUnREG4 LSU n Control Register 5 LSU nREG5 Field Descriptions LSUn Control Register 5 LSUnREG5Drbllinfo Hopcount Packettype LSUn Control Register 6 LSUnREG6 Field Descriptions LSUn Control Register 6 LSUnREG6Completioncode BSY Completionc Flowmask LSU Congestion Control Flow Mask n Lsuflowmasks n Txhdp Txcp Rxhdp Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP Transmit Queue Teardown Register Txqueueteardown QUEUE3FLOWMASK QUEUE2FLOWMASK QUEUE1FLOWMASK QUEUE0FLOWMASKQUEUE5FLOWMASK QUEUE4FLOWMASK QUEUE7FLOWMASK QUEUE6FLOWMASK Mask QUEUE15FLOWMASK QUEUE14FLOWMASK Receive Queue Teardown Register Rxqueueteardown Receive Queue Teardown Register Rxqueueteardown Receive Cppi Control Register Rxcppicntl Field Descriptions Receive Cppi Control Register Rxcppicntl 3NUMMSGS Txqueuemap3QUEUEPTR 2NUMMSGS 7QUEUEPTR 7NUMMSGS6NUMMSGS 6QUEUEPTR 11QUEUEPTR 11NUMMSGS10NUMMSGS 10QUEUEPTR 15QUEUEPTR 15NUMMSGS14NUMMSGS 14QUEUEPTR Mailbox-to-Queue Mapping Register Ln RXUMAPLn Mailbox-to-Queue Mapping Register Hn RXUMAPHn Flowcntlid Flow Control Table Entry Registers FLOWCNTLn Device Identity CAR Devid Field Descriptions Device Identity CAR Devid Device Information CAR Devinfo Field Descriptions Device Information CAR DevinfoDevicerev Vendor supply device revision Assembly Identity CAR Asblyid Field Descriptions Assembly Identity CAR Asblyid Assembly Information CAR Asblyinfo Field Descriptions Assembly Information CAR Asblyinfo Processing Element Features CAR Pefeat Field Descriptions Processing Element Features CAR Pefeat Source Operations CAR Srcop Field Descriptions Source Operations CAR Srcop Destination Operations CAR Destop Field Descriptions Destination Operations CAR Destop Extendedaddress Processing Element Logical Layer Control CSR PellctlIngcontrol Ressingcont Lcsba Local Configuration Space Base Address 0 CSR Lclcfghbar Local Configuration Space Base Address 1 CSR Lclcfgbar Local Configuration Space Base Address 1 CSR Lclcfgbar Base Device ID CSR Baseid Field Descriptions Base Device ID CSR Baseid Hostbasedeviceid Host Base Device ID Lock CSR HostbaseidlockHostbasede Viceid Componenttag Component Tag CSR ComptagComponent Tag CSR Comptag Field Descriptions Efid Efptr Port Link Time-Out Control CSR Spltctl Port Link Timeout Control CSR Spltctl Field Descriptions Port Response Time-Out Control CSR Sprtctl Port Response Time-Out Control CSR Sprtctl Port General Control CSR Spgenctl Field Descriptions Port General Control CSR Spgenctl Command Port Link Maintenance Request CSR n SPnLMREQ Port Link Maintenance Response CSR n SPnLMRESP Port Local AckID Status CSR n SPnACKIDSTAT Port Error and Status CSR n SPnERRSTAT Field Descriptions Port Error and Status CSR n SPnERRSTAT Lized PortokPortuninitia Port Control CSR n SPnCTL Field Descriptions Port Control CSR n SPnCTL Nable Port Control CSR n SP nCTL Field Descriptions Error Reporting Block Header Errrptbh Field Descriptions Error Reporting Block Header Errrptbh Logical/Transport Layer Error Detect CSR Errdet Logical/Transport Layer Error Enable CSR Erren 50 bit addresses Logical/Transport Layer High Address Capture CSR HaddrcaptADDRESS6332 Xamsbs Logical/Transport Layer Address Capture CSR AddrcaptADDRESS313 Msbdestid Destid Logical/Transport Layer Device ID Capture CSR IdcaptMsbsourceid Sourceid Msbdestid Ftype Ttype Msginfo Logical/Transport Layer Control Capture CSR CtrlcaptImpspecific Ftype Port-Write Target Device ID CSR Pwtgtid Field Descriptions Port-Write Target Device ID CSR PwtgtidDeviceidmsb Deviceid Port Error Detect CSR n SPnERRDET Field Descriptions Port Error Detect CSR n SPnERRDET Port Error Rate Enable CSR n SPnRATEEN Field Descriptions Port Error Rate Enable CSR n SPnRATEEN Port n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0 CAPTURE0 CAPTURE0 CAPTURE1 CAPTURE1 CAPTURE2 CAPTURE2 CAPTURE3 CAPTURE3 Port Error Rate CSR n SPnERRRATE Field Descriptions Port Error Rate CSR n SPnERRRATE Port Error Rate Threshold CSR n SPnERRTHRESH Discoverytimer Port IP Discovery Timer in 4x mode SpipdiscoverytimerPwtimer Discoveryti Port IP Mode CSR Spipmode Field Descriptions Port IP Mode CSR Spipmode Rsten Port IP Mode CSR Spipmode Field Descriptions Prescale Serial Port IP Prescalar IpprescalSerial Port IP Prescalar Ipprescal Field Descriptions Pwcapt Port-Write-In Capture CSR n SPIPPWINCAPTn Portid Port Reset Option CSR n SPnRSTOPTPort Reset Option CSR n SP nRSTOPT Field Descriptions Port Control Independent Register n SPnCTLINDEP Maxretryer MaxretryenMaxretryth Irqen Silencetimer Port Silence Timer n SPnSILENCETIMERPort Silence Timer n SPnSILENCETIMER Field Descriptions Multevntcs Multevntcs Port Control Symbol Transmit n SP nCSTX Field Descriptions Port Control Symbol Transmit n SPnCSTX Important Notice