Texas Instruments TMS320C645x manual LSU3REG1

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			SRIO Registers
	Table 28. Serial Rapid IO (SRIO) Registers (continued)
Offset	Acronym	Register Description	Section
0x0444	LSU3_REG1	LSU3 Control Register 1	Section 5.42
0x0448	LSU3_REG2	LSU3 Control Register 2	Section 5.43
0x044C	LSU3_REG3	LSU3 Control Register 3	Section 5.44
0x0450	LSU3_REG4	LSU3 Control Register 4	Section 5.45
0x0454	LSU3_REG5	LSU3 Control Register 5	Section 5.46
0x0458	LSU3_REG6	LSU3 Control Register 6	Section 5.47
0x045C	LSU3_FLOW_MASK	Core 2 LSU Congestion Control Flow Mask Register	Section 5.48
	S2
0x0460	LSU4_REG0	LSU4 Control Register 0	Section 5.41
0x0464	LSU4_REG1	LSU4 Control Register 1	Section 5.42
0x0468	LSU4_REG2	LSU4 Control Register 2	Section 5.43
0x046C	LSU4_REG3	LSU4 Control Register 3	Section 5.44
0x0470	LSU4_REG4	LSU4 Control Register 4	Section 5.45
0x0474	LSU4_REG5	LSU4 Control Register 5	Section 5.46
0x0478	LSU4_REG6	LSU4 Control Register 6	Section 5.47
0x047C	LSU4_FLOW_MASK	Core 3 LSU Congestion Control Flow Mask Register	Section 5.48
	S3
0x0500	QUEUE0_TXDMA_H	Queue Transmit DMA Head Descriptor Pointer Register 0	Section 5.49
	DP
0x0504	QUEUE1_TXDMA_H	Queue Transmit DMA Head Descriptor Pointer Register 1	Section 5.49
	DP
0x0508	QUEUE2_TXDMA_H	Queue Transmit DMA Head Descriptor Pointer Register 2	Section 5.49
	DP
0x050C	QUEUE3_TXDMA_H	Queue Transmit DMA Head Descriptor Pointer Register 3	Section 5.49
	DP
0x0510	QUEUE4_TXDMA_H	Queue Transmit DMA Head Descriptor Pointer Register 4	Section 5.49
	DP
0x0514	QUEUE5_TXDMA_H	Queue Transmit DMA Head Descriptor Pointer Register 5	Section 5.49
	DP
0x0518	QUEUE6_TXDMA_H	Queue Transmit DMA Head Descriptor Pointer Register 6	Section 5.49
	DP
0x051C	QUEUE7_TXDMA_H	Queue Transmit DMA Head Descriptor Pointer Register 7	Section 5.49
	DP
0x0520	QUEUE8_TXDMA_H	Queue Transmit DMA Head Descriptor Pointer Register 8	Section 5.49
	DP
0x0524	QUEUE9_TXDMA_H	Queue Transmit DMA Head Descriptor Pointer Register 9	Section 5.49
	DP
0x0528	QUEUE10_TXDMA_	Queue Transmit DMA Head Descriptor Pointer Register 10	Section 5.49
	HDP
0x052C	QUEUE11_TXDMA_	Queue Transmit DMA Head Descriptor Pointer Register 11	Section 5.49
	HDP
0x0530	QUEUE12_TXDMA_	Queue Transmit DMA Head Descriptor Pointer Register 12	Section 5.49
	HDP
0x0534	QUEUE13_TXDMA_	Queue Transmit DMA Head Descriptor Pointer Register 13	Section 5.49
	HDP
0x0538	QUEUE14_TXDMA_	Queue Transmit DMA Head Descriptor Pointer Register 14	Section 5.49
	HDP
0x053C	QUEUE15_TXDMA_	Queue Transmit DMA Head Descriptor Pointer Register 15	Section 5.49
	HDP
0x0580	QUEUE0_TXDMA_C	Queue Transmit DMA Completion Pointer Register 0	Section 5.50
	P

SPRU976 –March 2006	Serial RapidIO (SRIO)	91
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