Manuals
/
Texas Instruments
/
Computer Equipment
/
Network Card
Texas Instruments
TMS320C645x
manual
Submit Documentation Feedback
Models:
TMS320C645x
1
2
218
218
Download
218 pages
2.08 Kb
1
2
3
4
5
6
7
8
Block Diagram
Emulation Control Signals
Timer
Control Symbols
Maintenance
Serdes and its Configurations
Reset and Power Down State
Command
Assembly Identity CAR Asblyid
Bootload Capability
Page 2
Image 2
2
SPRU976
–March
2006
Submit Documentation Feedback
Page 1
Page 3
Page 2
Image 2
Page 1
Page 3
Contents
Users Guide
Submit Documentation Feedback
Contents
Errrstevnticrr
Base Device ID CSR Baseid
List of Figures
Load/Store Module Interrupt Condition Routing Registers
150
Port Error Rate Threshold CSR n SP n Errthresh
List of Tables
LSUn Control Register 0 LSUnREG0 Field Descriptions
Base Device ID CSR Baseid Field Descriptions
Read This First
General RapidIO System
RapidIO Architectural Hierarchy
Overview
RapidIO Interconnect Architecture
3 1x/4x LP-Serial
RapidIO Feature Support in Srio
Features Supported in Srio
External Devices Requirements
Features Not Supported
Standards
RapidIO Documents and Links
Overview
Peripheral Data Flow
Srio Packets
Operation Sequence
Operation Sequence
Example Packet Streaming Write
Control Symbols
4x RapidIO Packet Data Stream Streaming-Write Class
Ftype Ttype Packet Type
Srio Packet Ftype/Ttype
Packet Type
Functional Operation
Srio Pins
Block Diagram
Pin Description
Srio Conceptual Block Diagram
Bits of Serdescfg nCNTL Register 0x120 0x12c
Serdes and its Configurations
Enabling the PLL
Bit Name Value Description
Rate Bit Effects
Bits of Serdescfg nCNTL Register 0x120 0x12c
Line Rate versus PLL Output Clock Frequency
Bits of Serdescfgrx nCNTL Registers
Frequency Range versus MPY
Enabling the Receiver
Bit Field Value Description 1514
Disabled. Loss of signal detection disabled
Bits of SERDESCFGRXnCNTL Registers
Bits of Serdescfgtx nCNTL Registers
EQ Bits
Enabling the Transmitter
CFGRX2219 Low Freq Gain
DE Bits
Bits of Serdescfgtx nCNTL Registers
Swing Bits
Serdes Configuration Example
DirectIO
Control/Command Register Field Mapping
RapidIO Packet Header Field
Status Field Function
Control/Command Register RapidIO Packet Header Field
Status Fields
BSY
LSU Registers Timing
Example Burst Nwriter
Detailed Data Path Description
TX Operation
Write Transactions
Read Transactions
Segmentation
RX Operation
Reset and Power Down State
Message Passing
Cppi RX Scheme for RapidIO
Queue Mapping Table Address Offset 0x0800 0x08FC
Queue Mapping Register Rxumapl n
Bit Name Description
RX Buffer Descriptor Fields
RX Buffer Descriptor Field Descriptions
Field Description
RX Buffer Descriptor Field Descriptions
Field Description
RX Cppi Mode Explanation
Cppi Boundary Diagram
TX Buffer Descriptor Fields
TX Buffer Descriptor Field Definitions
Uses this bit to reclaim buffers
Ssize
TXQUEUECNTL1- Address Offset 0x7E4
Name Bit Access Reset Value Description
TXQUEUECNTL0- Address Offset 0x7E0
TXQUEUECNTL2- Address Offset 0x7E8
TXQueueMap10 2316 0x0A
Detailed Data Path Description
TX Operation
Message Passing Software Requirements
RX Operation
RX Buffer Descriptor
Initialization Example
Queue Mapping
TX Buffer Descriptor
NDP
Maintenance
Start Message Passing
Doorbell
Doorbell Operation
Congestion Control
Detailed Description
Name Bit
Transmit Source Flow Control Masks
Configuration Bus Example
Endianness
Reset
DMA Example
BLK8ENSTA BLK7ENSTA
Reset Summary
Enable and Enable Status Registers
Gblen
Enable and Enable Status Bit Field Descriptions
Enstat
BLK0EN
BLK2EN
BLK1EN
BLK1ENSTAT
BLK2ENSTAT
BLK8ENSTAT
Software Shutdown Details
Emulation
Peren Soft Free
Peren
Emulation Control Signals
Enabling the Srio Peripherals
Set Device ID Registers
11.2 PLL, Ports, Device ID and Data Rate Initializations
Peripheral Initializations
Assert the Peren bit to enable logical layer data flow
Read register to check portx1-4 OK bit
Bootload Data Movement
Bootload Capability
Configuration
Device Wakeup
MSG REQ
ERR
CPU Interrupts
General Description
Interrupt Condition Control Registers
Interrupt Source Configuration Options
Where ICS0 Doorbell1, bit 0, through ICS15 Doorbell1, bit
Interrupt Conditions
LSU Interrupt Condition Clear Registers Iccr Address Offset
ICC11 ICC10 ICC9 ICC8
ICS11 ICS10 ICS9 ICS8
ICS2 ICS1 ICS0
ICC2 ICC1 ICC0
Interrupt Condition Routing Options
DOORBELL0ICRR2 Address Offset
LSUICRR3 Address Offset 0x02EC
LSUICRR1 Address Offset 0x02E4
LSUICRR2 Address Offset 0x02E8
ERRRSTEVNTICRR3 Address Offset 0x02F8
Interrupt Status Decode Registers
ERRRSTEVNTICRR2 Address Offset 0x02F4
ICR2 ICR1 ICR0
Sharing of Isdr Bits
ISDR3 ISDR2 ISDR1 ISDR9 ISDR8 ISDR7 ISDR6 ISDR5 ISDR4 ISDR0
Interrupt Generation
Interrupt Pacing
Interrupt Handling
INTDSTnRATECNTL Interrupt Rate Control Register
Interrupt Conditions
Offset Acronym Register Description
Introduction
Serial Rapid IO Srio Registers
Serial Rapid IO Srio Registers
Offset Acronym Register Description
RR2
LSUICRR3
Errrstevntic
RR3
LSU3REG1
QUEUE3TXDMAC
QUEUE1TXDMAC
QUEUE2TXDMAC
QUEUE4TXDMAC
QUEUE12RXDMA
SKS7
Txcppiflowma
SKS6
Rxqueuetear
RXUMAPL19
RXUMAPL18
RXUMAPH18
RXUMAPH19
Pefeat
Asblyid
Asblyinfo
Srcop
SP0ERRCAPTDB
SP0ERRATTRCA
PTDBG0
SP0ERRRATE
SP3ERRTHRESH
Timer
SP3ERRRATE
Spipdiscovery
Type
Peripheral Identification Register PID
Peripheral ID Register PID Field Descriptions
Class REV
Pere Soft Free
Peripheral Control Register PCR
Peripheral Control Register PCR Field Descriptions
Bit Field
Peripheral Settings Control Register Persetcntl
Prescalerse
Cbatranspr
1XMODE
Lect
ENPLL1
ENPLL3
ENPLL2
Peripheral Global Enable Register Gblen
Peripheral Global Enable Register Gblen Field Descriptions
ENS
Peripheral Global Enable Status Register Gblenstat
GBL
TAT
Block n Enable Register BLKnEN
Block n Enable Register BLKnEN Field Descriptions
Block n Enable Status Register BLKnENSTAT
Block n Enable Status Register BLKnENSTAT
8BNODEID
RapidIO DEVICEID1 Register DEVICEIDREG1
RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions
16BNODEID
RapidIO DEVICEID2 Register DEVICEIDREG2
RapidIO DEVICEID2 Register DEVICEIDREG2 Field Descriptions
Packet Forwarding Register n for 16b DeviceIDs PF16BCNTLn
Packet Forwarding Register n for 8b DeviceIDs PF8BCNTLn
CDR LOS Align
Term Invpa Rate Buswidth
CFGRX2219 Low Freq Gain Zero Freq at e28 min
Entx
Enft
Swing Invpa Rate Buswidth
CFGTX119 Amplitude mV dfpp
Swing Bits
DE Bits
CFGTX1512 Amplitude Reduction
RIOCLK/RIOCLK
Serdes Macro Configuration Register n SERDESCFGnCNTL
MPY Enpll
MPY
DOORBELLn Interrupt Status Register DOORBELLnICSR
DOORBELLn Interrupt Status Register DOORBELLnICSR
DOORBELLn Interrupt Clear Register DOORBELLnICCR
DOORBELLn Interrupt Clear Register DOORBELLnICCR
RX Cppi Interrupt Status Register Rxcppiicsr
RX Cppi Interrupt Status Register Rxcppiicsr
RX Cppi Interrupt Clear Register Rxcppiiccr
RX Cppi Interrupt Clear Register Rxcppiiccr
TX Cppi Interrupt Status Register Txcppiicsr
TX Cppi Interrupt Status Register Txcppiicsr
TX Cppi Interrupt Clear Register Txcppiiccr
TX Cppi Interrupt Clear Register Txcppiiccr
ICS31-0 Load/Store module interrupt condition status bits
LSU Status Interrupt Register Lsuicsr
LSU Status Interrupt Register Lsuicsr Field Descriptions
ICS31-0 Load/Store module interrupt clear bits
LSU Clear Interrupt Register LSU Iccr
LSU Clear Interrupt Register LSU Iccr Field Descriptions
31-17
126
DOORBELLn Interrupt Condition Routing Register DOORBELLnICRR
128
RX Cppi Interrupt Condition Routing Register Rxcppi Icrr
ICR RX Cppi Interrupt condition routing bits
RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2
RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2
TX Cppi Interrupt Condition Routing Register Txcppi Icrr
ICR TX Cppi Interrupt condition routing bits
TX Cppi Interrupt Condition Routing Register Txcppi ICRR2
TX Cppi Interrupt Condition Routing Register Txcppi ICRR2
LSU Module Interrupt Condition Routing Register 0 LSUICRR0
ICR
LSU Module Interrupt Condition Routing Register 1 LSUICRR1
LSU Module Interrupt Condition Routing Register 1 LSUICRR1
LSU Module Interrupt Condition Routing Register 2 LSUICRR2
LSU Module Interrupt Condition Routing Register 2 LSUICRR2
LSU Module Interrupt Condition Routing Register 3 LSUICRR3
LSU Module Interrupt Condition Routing Register 3 LSUICRR3
Errrstevnticrr
Errrstevnticrr Field Descriptions
ERRRSTEVNTICRR2 Field Descriptions
ICR11
ERRRSTEVNTICRR3
ERRRSTEVNTICRR3 Field Descriptions
INTDSTn Interrupt Status Decode Registers INTDSTnDECODE
INTDSTn Interrupt Status Decode Registers INTDSTnDECODE
Countdown
INTDSTn Interrupt Rate Control Registers INTDSTnRATECNTL
Countdownvalue
Value
Addressmsb
LSUn Control Register 0 LSUnREG0
LSU n Control Register 0 LSU nREG0 Field Descriptions
Bit Ext address fields
LSUn Control Register 1 LSUnREG1
Addresslsbconfigoffset
Addresslsb Configoffse T
LSU n Control Register 1 LSU nREG1 Field Descriptions
Dspaddress
LSUn Control Register 2 LSUnREG2
LSU n Control Register 2 LSU nREG2 Field Descriptions
32b DSP byte address
Bytecount
LSUn Control Register 3 LSUnREG3
LSU n Control Register 3 LSU nREG3 Field Descriptions
LSUn Control Register 4 LSUnREG4
LSUn Control Register 4 LSUnREG4 Field Descriptions
Drbllinfo
LSUn Control Register 5 LSUnREG5
LSU n Control Register 5 LSU nREG5 Field Descriptions
Hopcount Packettype
Completioncode BSY
LSUn Control Register 6 LSUnREG6
LSUn Control Register 6 LSUnREG6 Field Descriptions
Completionc
LSU Congestion Control Flow Mask n Lsuflowmasks n
Flowmask
Txhdp
Txcp
Rxhdp
Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP
Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP
Transmit Queue Teardown Register Txqueueteardown
QUEUE5FLOWMASK QUEUE4FLOWMASK
QUEUE1FLOWMASK QUEUE0FLOWMASK
QUEUE3FLOWMASK QUEUE2FLOWMASK
QUEUE7FLOWMASK QUEUE6FLOWMASK
QUEUE15FLOWMASK QUEUE14FLOWMASK
Mask
Receive Queue Teardown Register Rxqueueteardown
Receive Queue Teardown Register Rxqueueteardown
Receive Cppi Control Register Rxcppicntl
Receive Cppi Control Register Rxcppicntl Field Descriptions
3QUEUEPTR
Txqueuemap
3NUMMSGS
2NUMMSGS
6NUMMSGS
7NUMMSGS
7QUEUEPTR
6QUEUEPTR
10NUMMSGS
11NUMMSGS
11QUEUEPTR
10QUEUEPTR
14NUMMSGS
15NUMMSGS
15QUEUEPTR
14QUEUEPTR
Mailbox-to-Queue Mapping Register Ln RXUMAPLn
Mailbox-to-Queue Mapping Register Hn RXUMAPHn
Flow Control Table Entry Registers FLOWCNTLn
Flowcntlid
Device Identity CAR Devid
Device Identity CAR Devid Field Descriptions
Devicerev
Device Information CAR Devinfo
Device Information CAR Devinfo Field Descriptions
Vendor supply device revision
Assembly Identity CAR Asblyid
Assembly Identity CAR Asblyid Field Descriptions
Assembly Information CAR Asblyinfo
Assembly Information CAR Asblyinfo Field Descriptions
Processing Element Features CAR Pefeat
Processing Element Features CAR Pefeat Field Descriptions
Source Operations CAR Srcop
Source Operations CAR Srcop Field Descriptions
Destination Operations CAR Destop
Destination Operations CAR Destop Field Descriptions
Ingcontrol
Processing Element Logical Layer Control CSR Pellctl
Extendedaddress
Ressingcont
Local Configuration Space Base Address 0 CSR Lclcfghbar
Lcsba
Local Configuration Space Base Address 1 CSR Lclcfgbar
Local Configuration Space Base Address 1 CSR Lclcfgbar
Base Device ID CSR Baseid
Base Device ID CSR Baseid Field Descriptions
Hostbasede
Host Base Device ID Lock CSR Hostbaseidlock
Hostbasedeviceid
Viceid
Componenttag
Component Tag CSR Comptag
Component Tag CSR Comptag Field Descriptions
Efptr
Efid
Port Link Timeout Control CSR Spltctl Field Descriptions
Port Link Time-Out Control CSR Spltctl
Port Response Time-Out Control CSR Sprtctl
Port Response Time-Out Control CSR Sprtctl
Port General Control CSR Spgenctl
Port General Control CSR Spgenctl Field Descriptions
Port Link Maintenance Request CSR n SPnLMREQ
Command
Port Link Maintenance Response CSR n SPnLMRESP
Port Local AckID Status CSR n SPnACKIDSTAT
Port Error and Status CSR n SPnERRSTAT
Port Error and Status CSR n SPnERRSTAT Field Descriptions
Lized
Portok
Portuninitia
Port Control CSR n SPnCTL
Port Control CSR n SPnCTL Field Descriptions
Port Control CSR n SP nCTL Field Descriptions
Nable
Error Reporting Block Header Errrptbh
Error Reporting Block Header Errrptbh Field Descriptions
Logical/Transport Layer Error Detect CSR Errdet
Logical/Transport Layer Error Enable CSR Erren
50 bit addresses
Logical/Transport Layer High Address Capture CSR Haddrcapt
ADDRESS6332
Xamsbs
Logical/Transport Layer Address Capture CSR Addrcapt
ADDRESS313
Msbsourceid Sourceid
Logical/Transport Layer Device ID Capture CSR Idcapt
Msbdestid Destid
Msbdestid
Impspecific
Logical/Transport Layer Control Capture CSR Ctrlcapt
Ftype Ttype Msginfo
Ftype
Deviceidmsb
Port-Write Target Device ID CSR Pwtgtid
Port-Write Target Device ID CSR Pwtgtid Field Descriptions
Deviceid
Port Error Detect CSR n SPnERRDET
Port Error Detect CSR n SPnERRDET Field Descriptions
Port Error Rate Enable CSR n SPnRATEEN
Port Error Rate Enable CSR n SPnRATEEN Field Descriptions
Port n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0
CAPTURE0
CAPTURE0
CAPTURE1
CAPTURE1
CAPTURE2
CAPTURE2
CAPTURE3
CAPTURE3
Port Error Rate CSR n SPnERRRATE
Port Error Rate CSR n SPnERRRATE Field Descriptions
Port Error Rate Threshold CSR n SPnERRTHRESH
Pwtimer
Port IP Discovery Timer in 4x mode Spipdiscoverytimer
Discoverytimer
Discoveryti
Port IP Mode CSR Spipmode
Port IP Mode CSR Spipmode Field Descriptions
Port IP Mode CSR Spipmode Field Descriptions
Rsten
Prescale
Serial Port IP Prescalar Ipprescal
Serial Port IP Prescalar Ipprescal Field Descriptions
Port-Write-In Capture CSR n SPIPPWINCAPTn
Pwcapt
Portid
Port Reset Option CSR n SPnRSTOPT
Port Reset Option CSR n SP nRSTOPT Field Descriptions
Port Control Independent Register n SPnCTLINDEP
Maxretryth
Maxretryen
Maxretryer
Irqen
Silencetimer
Port Silence Timer n SPnSILENCETIMER
Port Silence Timer n SPnSILENCETIMER Field Descriptions
Multevntcs
Multevntcs
Port Control Symbol Transmit n SPnCSTX
Port Control Symbol Transmit n SP nCSTX Field Descriptions
Important Notice
Top
Page
Image
Contents