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SRIO Functional Description
So the general flow is as follows:
∙Previously, the control/command registers were written and the request packet was sent
∙Response Packet Type13, Trans != 0001b arrives at module interface, and is handled sequentially (not based on priority)
∙targetTID is examined to determine routing of a response to the appropriate core
∙The status field of the response packet is checked for ERROR, RETRY or DONE
∙If the field is DONE, it submits DMA bus request and transmits the payload (if any) to DSP address. If the field is ERROR/RETRY, it sets an interrupt
∙Command registers are released (BSY = 0)
∙Optional Interrupt to CPU notifying packet reception
2.3.3.4Reset and Power Down State
Upon reset, the Load/Store module must clear the command register fields and wait for a write by the CPU.
The Load/Store module can be powered down if the direct I/O protocol is not being supported in the application. For example, if the messaging protocol is being used for data transfers, powering down the Load/Store module will save power. In this situation, the command registers should be powered down and inaccessible. Clocks should be gated to these blocks while in the power down state.
2.3.4Message Passing
With message passing, a destination address is not specified. Instead, a mailbox identifier is used within the RapidIO packet. The mailbox is controlled and mapped to memory by the local (destination) device. The message passing within RapidIO specifies 4 mailbox locations. Each mailbox can contain 4 separate transactions (or letters), effectively providing 16 messages. Single packet messages provide 64 mailboxes with 4 letters, effectively providing 256 messages. Mailboxes can be defined for different data types or priorities. The advantage of message passing is that the source device does not require any knowledge of the destination device’s memory map. The DSP contains Buffer Descriptions Tables for each mailbox. These tables define a memory map and pointers for each mailbox. Messages are transferred to the appropriate memory locations via the DMA.
The CPPI (Communications Port Programming Interface) module serves as the incoming and outgoing message passing protocol engine.
The following rules exist for all CPPI traffic:
∙One buffer descriptor per message (each buffer descriptor consists of 4 words or 16 bytes)
∙Requires contiguous memory space for
–Fixed buffer sizes (configured to handle application'smax message size)
∙An ERROR response is sent if the RX message is too big for the allotted buffer sizes
–Subsequent ERROR responses will be sent for all segments of that message
∙An ERROR response is sent if the mailbox is not mapped, or mapped to a
∙An ERROR response is sent if the mailbox is mapped, but the queue is not initialized (RX DMA State HDP not written), or the queue is disabled (Teardown)
∙An ERROR response is sent if the RX buffer descriptor queue has no empty buffers (overflow)
∙
∙RETRY response will be issued to the first received segment of a
–Subsequent RETRY responses may have to be sent for received pipeline segments or additional pipelined messages to the same queue
∙Inorder message reception for dedicated flows is mode programmable
∙A queue is needed for each supported simultaneous
∙Supports a minimum of 1.25KB SRAM (64 buffer descriptors)
∙Transmit must be able to RETRY any given segment of a transmitted message
∙A Dest_id is equal to port for TX operations, the same Dest_Id is not accessible from multiple ports
40 | Serial RapidIO (SRIO) | SPRU976 |
