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SRIO Functional Description
RIO_LSUn_FLOW_MASKS (Address fsets: 0x043C,
Figure 28. Transmit Source Flow Control Masks
Reserved | LSU |
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RIO_TX_CPPI_FLOW_MASKS0 (Address fsets:
RIO_TX_CPPI_FLOW_MASKS1 (Address fsets:
RIO_TX_CPPI_FLOW_MASKS2 (Address fsets:
RIO_TX_CPPI_FLOW_MASKS3 (Address fsets:
R, | R/W, |
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TX | TX |
Flow | Flow |
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R/W, | R/W, |
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TX | TX |
Flow | Flow |
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R/W, | R/W, |
TX | TX |
Flow | Flow |
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R/W, | R/W, |
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TX | TX |
Flow | Flow |
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R/W, | R/W, |
RIO_TX_CPPI_FLOW_MASKS4 (Address fsets:
RIO_TX_CPPI_FLOW_MASKS5 (Address fsets:
RIO_TX_CPPI_FLOW_MASKS6 (Address fsets:
RIO_TX_CPPI_FLOW_MASKS7 (Address fsets:
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TX |
| TX |
Flow |
| Flow |
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R/W, |
| R/W, |
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TX | 1 | TX |
Flow |
| Flow |
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R/W, |
| R/W, |
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TX |
| TX |
Flow |
| Flow |
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R/W, |
| R/W, |
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TX |
| TX |
Flow |
| Flow |
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R/W, |
| R/W, |
Table 23. Transmit Source Flow Control Masks
| Name | Bit | Access | Reset Value | Description | |
| Flow Mask | 0 | R/W | 1b | 0b | – TX source doesn’t support Flow0 from table entry |
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| 1b | – TX source does support Flow0 from table entry |
| Flow Mask | 1 | R/W | 1b | 0b | – TX source doesn’t support Flow1 from table entry |
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| 1b | – TX source does support Flow1 from table entry |
| Flow Mask | 2 | R/W | 1b | 0b | – TX source doesn’t support Flow2 from table entry |
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| 1b | – TX source does support Flow2 from table entry |
| Flow Mask | 3 | R/W | 1b | 0b | – TX source doesn’t support Flow3 from table entry |
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| 1b | – TX source does support Flow3 from table entry |
| Flow Mask | 4 | R/W | 1b | 0b | – TX source doesn’t support Flow4 from table entry |
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| 1b | – TX source does support Flow4 from table entry |
| Flow Mask | 5 | R/W | 1b | 0b | – TX source doesn’t support Flow5 from table entry |
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| 1b | – TX source does support Flow5 from table entry |
| Flow Mask | 6 | R/W | 1b | 0b | – TX source doesn’t support Flow6 from table entry |
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| 1b | – TX source does support Flow6 from table entry |
| Flow Mask | 7 | R/W | 1b | 0b | – TX source doesn’t support Flow7 from table entry |
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| 1b | – TX source does support Flow7 from table entry |
| Flow Mask | 8 | R/W | 1b | 0b | – TX source doesn’t support Flow8 from table entry |
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| 1b | – TX source does support Flow8 from table entry |
| Flow Mask | 9 | R/W | 1b | 0b | – TX source doesn’t support Flow9 from table entry |
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| 1b | – TX source does support Flow9 from table entry |
| Flow Mask | 10 | R/W | 1b | 0b | – TX source doesn’t support Flow10 from table entry |
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| 1b | – TX source does support Flow10 from table entry |
| Flow Mask | 11 | R/W | 1b | 0b | – TX source doesn’t support Flow11 from table entry |
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| 1b | – TX source does support Flow11 from table entry |
| Flow Mask | 12 | R/W | 1b | 0b | – TX source doesn’t support Flow12 from table entry |
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| 1b | – TX source does support Flow12 from table entry |
| Flow Mask | 13 | R/W | 1b | 0b | – TX source doesn’t support Flow13 from table entry |
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| 1b | – TX source does support Flow13 from table entry |
| Flow Mask | 14 | R/W | 1b | 0b | – TX source doesn’t support Flow14 from table entry |
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| 1b | – TX source does support Flow14 from table entry |
| Flow Mask | 15 | R/W | 1b | 0b | – TX source doesn’t support Flow15 from table entry |
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| 1b | – TX source does support Flow15 from table entry |
62 | Serial RapidIO (SRIO) |
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| SPRU976 | |
