![](/images/new-backgrounds/1206494/206494295x1.webp)
www.ti.com
SRIO Registers
5.47LSUn Control Register 6 (LSUn_REG6)
There are four of these registers, one for each LSU.
Figure 103. LSUn Control Register 6 (LSUn_REG6)
|
| |
| Reserved |
|
|
| |
LEGEND: R = Read only; |
|
|
0 | ||
Reserved | COMPLETION_CODE | BSY |
R- | ||
|
| 0x00 |
LEGEND: R = Read only;
Table 77. LSUn Control Register 6 (LSUn_REG6) Field Descriptions
Bit | Field | Value | Description |
Reserved |
| Reserved | |
COMPLETION_C |
| Indicates the status of the pending command. | |
| ODE |
|
|
|
| 000b | Transaction complete, No Errors |
|
| 001b | Transaction Timeout occurred on |
|
| 010 b | Transaction complete, Packet not sent due to flow control blockade (Xoff) |
|
| 011b | Transaction complete, |
|
|
| response payload length was in error |
|
| 100b | Transaction complete, Packet not sent due to unsupported transaction type or invalid programming |
|
|
| encoding for one or more LSU register fields |
|
| 101b | DMA data transfer error |
|
| 110b | "Retry" DOORBELL response received, or Atomic |
|
|
| use) |
|
| 111b | Transaction complete, Packet not sent due to unavailable outbound credit at given priority |
0 | BSY |
| Indicates status of the command registers. |
|
| 0b | Command registers are available(writable) for next set of transfer descriptors |
|
| 1b | Command registers are busy with current transfer |
148 | Serial RapidIO (SRIO) | SPRU976 |
|
| Submit Documentation Feedback |