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SRIO Functional Description

Figure 8. SRIO Conceptual Block Diagram

DMA bus

Load/store

 

Memory

 

 

unit

 

TXU

access

 

RXU

 

Tx

 

Messaging

(MAU)

Messaging

 

Maintenance

 

Rx

 

 

 

 

 

 

 

 

 

4.5

Tx

4.5

Tx

Queue

 

 

shared

shared

 

 

handle

 

 

buffer

buffer

 

 

 

 

128-bit

 

 

 

 

 

 

TX

fering

 

 

 

Logical

 

32

 

 

 

Transaction

 

 

 

 

layer

8

fers

 

 

 

mapping

 

 

 

buffers

32

fers

 

 

 

 

 

 

 

 

 

 

Port

 

Port

 

Port

 

Port

Physical

 

 

 

 

 

 

 

 

8

TX

8

TX

8

TX

8

TX

layer

buffers

8

 

8

 

8

 

8

 

 

 

 

 

 

4x

 

 

 

 

 

 

 

 

data

 

 

 

 

 

 

 

 

SERDES

SERDES

SERDES

SERDES

 

 

 

 

 

 

 

 

 

SERDES

 

 

 

 

 

 

 

 

differential

 

 

 

 

 

 

 

 

signals

SPRU976 –March 2006

Serial RapidIO (SRIO)

25

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Texas Instruments TMS320C645x manual Srio Conceptual Block Diagram