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SRIO Functional Description
Figure 8. SRIO Conceptual Block Diagram
DMA bus
Load/store |
| Memory |
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unit |
| TXU | access |
| RXU |
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Tx |
| Messaging | (MAU) | Messaging |
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Maintenance |
| Rx |
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| 4.5 | Tx | 4.5 | Tx | Queue |
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| shared | shared |
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| handle |
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| buffer | buffer |
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| TX | fering |
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| Logical |
| 32 |
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| Transaction | |
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8 | fers |
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| mapping | |
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32 | fers |
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| Port |
| Port |
| Port |
| Port | Physical | |
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8 | TX | 8 | TX | 8 | TX | 8 | TX | layer | |
buffers | |||||||||
8 |
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4x |
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data |
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SERDES | SERDES | SERDES | SERDES |
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| SERDES | |
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| differential | |
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| signals |
SPRU976 | Serial RapidIO (SRIO) | 25 |