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SRIO Registers

5.50Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP)

There are sixteen of these registers.

Figure 106. Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP)

31-16

TX_CP

RW-0x00

LEGEND: R = Read only; -n= value after reset

15-0

TX_CP

RW-0x00

LEGEND: R = Read only; -n= value after reset

Table 80. Queue Transmit DMA Completion Pointer Registers (QUEUEn_TXDMA_CP) Field

Descriptions

Bit	Field	Value Description
31-0	TX_CP	This field is the host memory address for the transmit queue completion pointer. This register is
		written by the host with the buffer descriptor address for the last buffer processed by the host
		during interrupt processing. The port uses the value written to determine if the interrupt should be
		deasserted.

SPRU976 –March 2006	Serial RapidIO (SRIO)	151
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Texas Instruments TMS320C645x manual Txcp

Contents

Users Guide Submit Documentation Feedback Contents Errrstevnticrr Base Device ID CSR Baseid List of Figures Load/Store Module Interrupt Condition Routing Registers 150 Port Error Rate Threshold CSR n SP n Errthresh List of Tables LSUn Control Register 0 LSUnREG0 Field Descriptions Base Device ID CSR Baseid Field Descriptions Read This First RapidIO Architectural Hierarchy General RapidIO System Overview 3 1x/4x LP-Serial RapidIO Interconnect Architecture Features Supported in Srio RapidIO Feature Support in Srio RapidIO Documents and Links Features Not SupportedStandards External Devices Requirements Peripheral Data Flow Overview Operation Sequence Srio Packets Example Packet Streaming Write Operation Sequence 4x RapidIO Packet Data Stream Streaming-Write Class Control Symbols Packet Type Srio Packet Ftype/TtypeFtype Ttype Packet Type Pin Description Srio PinsBlock Diagram Functional Operation Srio Conceptual Block Diagram Bit Name Value Description Serdes and its ConfigurationsEnabling the PLL Bits of Serdescfg nCNTL Register 0x120 0x12c Line Rate versus PLL Output Clock Frequency Bits of Serdescfg nCNTL Register 0x120 0x12cRate Bit Effects Enabling the Receiver Frequency Range versus MPYBits of Serdescfgrx nCNTL Registers Bits of SERDESCFGRXnCNTL Registers Disabled. Loss of signal detection disabledBit Field Value Description 1514 CFGRX2219 Low Freq Gain EQ BitsEnabling the Transmitter Bits of Serdescfgtx nCNTL Registers Swing Bits Bits of Serdescfgtx nCNTL RegistersDE Bits DirectIO Serdes Configuration Example RapidIO Packet Header Field Control/Command Register Field Mapping BSY Control/Command Register RapidIO Packet Header FieldStatus Fields Status Field Function LSU Registers Timing Detailed Data Path Description Example Burst Nwriter Write Transactions TX Operation Read Transactions RX Operation Segmentation Message Passing Reset and Power Down State Cppi RX Scheme for RapidIO Queue Mapping Table Address Offset 0x0800 0x08FC Bit Name Description Queue Mapping Register Rxumapl n RX Buffer Descriptor Fields Field Description RX Buffer Descriptor Field Descriptions Field Description RX Buffer Descriptor Field Descriptions RX Cppi Mode Explanation Cppi Boundary Diagram TX Buffer Descriptor Field Definitions TX Buffer Descriptor Fields Uses this bit to reclaim buffers Ssize TXQUEUECNTL2- Address Offset 0x7E8 Name Bit Access Reset Value DescriptionTXQUEUECNTL0- Address Offset 0x7E0 TXQUEUECNTL1- Address Offset 0x7E4 TXQueueMap10 2316 0x0A Detailed Data Path Description RX Operation Message Passing Software RequirementsTX Operation Queue Mapping Initialization ExampleRX Buffer Descriptor NDP TX Buffer Descriptor Start Message Passing Maintenance Doorbell Operation Doorbell Detailed Description Congestion Control Name Bit Transmit Source Flow Control Masks Endianness Configuration Bus Example DMA Example Reset Enable and Enable Status Registers Reset SummaryBLK8ENSTA BLK7ENSTA BLK0EN Enable and Enable Status Bit Field DescriptionsEnstat Gblen BLK2ENSTAT BLK1ENBLK1ENSTAT BLK2EN Peren Soft Free Software Shutdown DetailsEmulation BLK8ENSTAT Enabling the Srio Peripherals Emulation Control SignalsPeren Peripheral Initializations 11.2 PLL, Ports, Device ID and Data Rate InitializationsSet Device ID Registers Read register to check portx1-4 OK bit Assert the Peren bit to enable logical layer data flow Device Wakeup Bootload CapabilityConfiguration Bootload Data Movement ERR MSG REQ General Description CPU Interrupts Interrupt Condition Control Registers Interrupt Source Configuration Options Where ICS0 Doorbell1, bit 0, through ICS15 Doorbell1, bit Interrupt Conditions LSU Interrupt Condition Clear Registers Iccr Address Offset ICC2 ICC1 ICC0 ICS11 ICS10 ICS9 ICS8ICS2 ICS1 ICS0 ICC11 ICC10 ICC9 ICC8 DOORBELL0ICRR2 Address Offset Interrupt Condition Routing Options LSUICRR2 Address Offset 0x02E8 LSUICRR1 Address Offset 0x02E4LSUICRR3 Address Offset 0x02EC ICR2 ICR1 ICR0 Interrupt Status Decode RegistersERRRSTEVNTICRR2 Address Offset 0x02F4 ERRRSTEVNTICRR3 Address Offset 0x02F8 Sharing of Isdr Bits Interrupt Pacing Interrupt GenerationISDR3 ISDR2 ISDR1 ISDR9 ISDR8 ISDR7 ISDR6 ISDR5 ISDR4 ISDR0 INTDSTnRATECNTL Interrupt Rate Control Register Interrupt Handling Interrupt Conditions Serial Rapid IO Srio Registers IntroductionOffset Acronym Register Description Offset Acronym Register Description Serial Rapid IO Srio Registers RR3 LSUICRR3Errrstevntic RR2 LSU3REG1 QUEUE4TXDMAC QUEUE1TXDMACQUEUE2TXDMAC QUEUE3TXDMAC QUEUE12RXDMA Rxqueuetear TxcppiflowmaSKS6 SKS7 RXUMAPH19 RXUMAPL18RXUMAPH18 RXUMAPL19 Srcop AsblyidAsblyinfo Pefeat SP0ERRRATE SP0ERRATTRCAPTDBG0 SP0ERRCAPTDB Spipdiscovery TimerSP3ERRRATE SP3ERRTHRESH Class REV Peripheral Identification Register PIDPeripheral ID Register PID Field Descriptions Type Bit Field Peripheral Control Register PCRPeripheral Control Register PCR Field Descriptions Pere Soft Free Peripheral Settings Control Register Persetcntl Lect Cbatranspr1XMODE Prescalerse ENPLL2 ENPLL3ENPLL1 Peripheral Global Enable Register Gblen Field Descriptions Peripheral Global Enable Register Gblen TAT Peripheral Global Enable Status Register GblenstatGBL ENS Block n Enable Register BLKnEN Field Descriptions Block n Enable Register BLKnEN Block n Enable Status Register BLKnENSTAT Block n Enable Status Register BLKnENSTAT 16BNODEID RapidIO DEVICEID1 Register DEVICEIDREG1RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions 8BNODEID RapidIO DEVICEID2 Register DEVICEIDREG2 Field Descriptions RapidIO DEVICEID2 Register DEVICEIDREG2 Packet Forwarding Register n for 16b DeviceIDs PF16BCNTLn Packet Forwarding Register n for 8b DeviceIDs PF8BCNTLn Term Invpa Rate Buswidth CDR LOS Align CFGRX2219 Low Freq Gain Zero Freq at e28 min Swing Invpa Rate Buswidth EnftEntx CFGTX1512 Amplitude Reduction Swing BitsDE Bits CFGTX119 Amplitude mV dfpp MPY Serdes Macro Configuration Register n SERDESCFGnCNTLMPY Enpll RIOCLK/RIOCLK DOORBELLn Interrupt Status Register DOORBELLnICSR DOORBELLn Interrupt Status Register DOORBELLnICSR DOORBELLn Interrupt Clear Register DOORBELLnICCR DOORBELLn Interrupt Clear Register DOORBELLnICCR RX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Clear Register Rxcppiiccr RX Cppi Interrupt Clear Register Rxcppiiccr TX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Clear Register Txcppiiccr TX Cppi Interrupt Clear Register Txcppiiccr LSU Status Interrupt Register Lsuicsr Field Descriptions LSU Status Interrupt Register LsuicsrICS31-0 Load/Store module interrupt condition status bits LSU Clear Interrupt Register LSU Iccr Field Descriptions LSU Clear Interrupt Register LSU IccrICS31-0 Load/Store module interrupt clear bits 31-17 126 DOORBELLn Interrupt Condition Routing Register DOORBELLnICRR 128 ICR RX Cppi Interrupt condition routing bits RX Cppi Interrupt Condition Routing Register Rxcppi Icrr RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2 RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2 ICR TX Cppi Interrupt condition routing bits TX Cppi Interrupt Condition Routing Register Txcppi Icrr TX Cppi Interrupt Condition Routing Register Txcppi ICRR2 TX Cppi Interrupt Condition Routing Register Txcppi ICRR2 ICR LSU Module Interrupt Condition Routing Register 0 LSUICRR0 LSU Module Interrupt Condition Routing Register 1 LSUICRR1 LSU Module Interrupt Condition Routing Register 1 LSUICRR1 LSU Module Interrupt Condition Routing Register 2 LSUICRR2 LSU Module Interrupt Condition Routing Register 2 LSUICRR2 LSU Module Interrupt Condition Routing Register 3 LSUICRR3 LSU Module Interrupt Condition Routing Register 3 LSUICRR3 Errrstevnticrr Field Descriptions Errrstevnticrr ICR11 ERRRSTEVNTICRR2 Field Descriptions ERRRSTEVNTICRR3 Field Descriptions ERRRSTEVNTICRR3 INTDSTn Interrupt Status Decode Registers INTDSTnDECODE INTDSTn Interrupt Status Decode Registers INTDSTnDECODE Value INTDSTn Interrupt Rate Control Registers INTDSTnRATECNTLCountdownvalue Countdown Bit Ext address fields LSUn Control Register 0 LSUnREG0LSU n Control Register 0 LSU nREG0 Field Descriptions Addressmsb LSU n Control Register 1 LSU nREG1 Field Descriptions AddresslsbconfigoffsetAddresslsb Configoffse T LSUn Control Register 1 LSUnREG1 32b DSP byte address LSUn Control Register 2 LSUnREG2LSU n Control Register 2 LSU nREG2 Field Descriptions Dspaddress LSU n Control Register 3 LSU nREG3 Field Descriptions LSUn Control Register 3 LSUnREG3Bytecount LSUn Control Register 4 LSUnREG4 Field Descriptions LSUn Control Register 4 LSUnREG4 Hopcount Packettype LSUn Control Register 5 LSUnREG5LSU n Control Register 5 LSU nREG5 Field Descriptions Drbllinfo Completionc LSUn Control Register 6 LSUnREG6LSUn Control Register 6 LSUnREG6 Field Descriptions Completioncode BSY Flowmask LSU Congestion Control Flow Mask n Lsuflowmasks n Txhdp Txcp Rxhdp Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP Transmit Queue Teardown Register Txqueueteardown QUEUE7FLOWMASK QUEUE6FLOWMASK QUEUE1FLOWMASK QUEUE0FLOWMASKQUEUE3FLOWMASK QUEUE2FLOWMASK QUEUE5FLOWMASK QUEUE4FLOWMASK Mask QUEUE15FLOWMASK QUEUE14FLOWMASK Receive Queue Teardown Register Rxqueueteardown Receive Queue Teardown Register Rxqueueteardown Receive Cppi Control Register Rxcppicntl Field Descriptions Receive Cppi Control Register Rxcppicntl 2NUMMSGS Txqueuemap3NUMMSGS 3QUEUEPTR 6QUEUEPTR 7NUMMSGS7QUEUEPTR 6NUMMSGS 10QUEUEPTR 11NUMMSGS11QUEUEPTR 10NUMMSGS 14QUEUEPTR 15NUMMSGS15QUEUEPTR 14NUMMSGS Mailbox-to-Queue Mapping Register Ln RXUMAPLn Mailbox-to-Queue Mapping Register Hn RXUMAPHn Flowcntlid Flow Control Table Entry Registers FLOWCNTLn Device Identity CAR Devid Field Descriptions Device Identity CAR Devid Vendor supply device revision Device Information CAR DevinfoDevice Information CAR Devinfo Field Descriptions Devicerev Assembly Identity CAR Asblyid Field Descriptions Assembly Identity CAR Asblyid Assembly Information CAR Asblyinfo Field Descriptions Assembly Information CAR Asblyinfo Processing Element Features CAR Pefeat Field Descriptions Processing Element Features CAR Pefeat Source Operations CAR Srcop Field Descriptions Source Operations CAR Srcop Destination Operations CAR Destop Field Descriptions Destination Operations CAR Destop Ressingcont Processing Element Logical Layer Control CSR PellctlExtendedaddress Ingcontrol Lcsba Local Configuration Space Base Address 0 CSR Lclcfghbar Local Configuration Space Base Address 1 CSR Lclcfgbar Local Configuration Space Base Address 1 CSR Lclcfgbar Base Device ID CSR Baseid Field Descriptions Base Device ID CSR Baseid Viceid Host Base Device ID Lock CSR HostbaseidlockHostbasedeviceid Hostbasede Component Tag CSR Comptag Field Descriptions Component Tag CSR ComptagComponenttag Efid Efptr Port Link Time-Out Control CSR Spltctl Port Link Timeout Control CSR Spltctl Field Descriptions Port Response Time-Out Control CSR Sprtctl Port Response Time-Out Control CSR Sprtctl Port General Control CSR Spgenctl Field Descriptions Port General Control CSR Spgenctl Command Port Link Maintenance Request CSR n SPnLMREQ Port Link Maintenance Response CSR n SPnLMRESP Port Local AckID Status CSR n SPnACKIDSTAT Port Error and Status CSR n SPnERRSTAT Field Descriptions Port Error and Status CSR n SPnERRSTAT Portuninitia PortokLized Port Control CSR n SPnCTL Field Descriptions Port Control CSR n SPnCTL Nable Port Control CSR n SP nCTL Field Descriptions Error Reporting Block Header Errrptbh Field Descriptions Error Reporting Block Header Errrptbh Logical/Transport Layer Error Detect CSR Errdet Logical/Transport Layer Error Enable CSR Erren ADDRESS6332 Logical/Transport Layer High Address Capture CSR Haddrcapt50 bit addresses ADDRESS313 Logical/Transport Layer Address Capture CSR AddrcaptXamsbs Msbdestid Logical/Transport Layer Device ID Capture CSR IdcaptMsbdestid Destid Msbsourceid Sourceid Ftype Logical/Transport Layer Control Capture CSR CtrlcaptFtype Ttype Msginfo Impspecific Deviceid Port-Write Target Device ID CSR PwtgtidPort-Write Target Device ID CSR Pwtgtid Field Descriptions Deviceidmsb Port Error Detect CSR n SPnERRDET Field Descriptions Port Error Detect CSR n SPnERRDET Port Error Rate Enable CSR n SPnRATEEN Field Descriptions Port Error Rate Enable CSR n SPnRATEEN Port n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0 CAPTURE0 CAPTURE0 CAPTURE1 CAPTURE1 CAPTURE2 CAPTURE2 CAPTURE3 CAPTURE3 Port Error Rate CSR n SPnERRRATE Field Descriptions Port Error Rate CSR n SPnERRRATE Port Error Rate Threshold CSR n SPnERRTHRESH Discoveryti Port IP Discovery Timer in 4x mode SpipdiscoverytimerDiscoverytimer Pwtimer Port IP Mode CSR Spipmode Field Descriptions Port IP Mode CSR Spipmode Rsten Port IP Mode CSR Spipmode Field Descriptions Serial Port IP Prescalar Ipprescal Field Descriptions Serial Port IP Prescalar IpprescalPrescale Pwcapt Port-Write-In Capture CSR n SPIPPWINCAPTn Port Reset Option CSR n SP nRSTOPT Field Descriptions Port Reset Option CSR n SPnRSTOPTPortid Port Control Independent Register n SPnCTLINDEP Irqen MaxretryenMaxretryer Maxretryth Port Silence Timer n SPnSILENCETIMER Field Descriptions Port Silence Timer n SPnSILENCETIMERSilencetimer Multevntcs Multevntcs Port Control Symbol Transmit n SP nCSTX Field Descriptions Port Control Symbol Transmit n SPnCSTX Important Notice