Port Control CSR n SPnCTL | Texas Instruments TMS320C645x specs

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SRIO Registers

5.85Port Control CSR n (SPn_CTL)

Each of the four ports is supported by a register of this type.

Figure 141. Port Control CSR n (SPn_CTL)

31-30	29-27	26-24	23	22	21	20	19		18-16
PORT_WIDTH INITIALIZED_PORT_WI PORT_WIDTH_OVERRI PORT OUTP					INPUT	ERRO	MULTI		Reserved
	DTH	DE	_DISA	UT_P	_POR R_CH		CAST
			BLE	ORT_	T_EN ECK_ _PAR
				ENAB	ABLE	DISAB	TICIP
				LE		LE	ANT
R-0x01	R-0x00	RW-0x00	RW-	RW-	RW-	RW-	RW-		R-0x00
			0x00	0x00	0x00	0x00	0x00
LEGEND: R = Read only; -n= value after reset
		15-4					3	2	1	0
		Reserved					STOP	DROP	PORT	PORT
							_POR	_PAC	_LOC	_TYPE
							T_FLD KET_E KOUT
							_ENC	NABL
							_ENA	E
							BLE
		R-0x00					RW-	RW-	RW-	R-
							0x00	0x00	0x00	0x01

LEGEND: R = Read only; -n= value after reset

Table 115. Port Control CSR n (SPn_CTL) Field Descriptions

Bit	Field	Value	Description
31-30 PORT_WIDTH			Hardware width of the port (read only). Only 00b is valid for SP1, SP2, and SP3
		00b	Single-lane port
		01b	Four-lane port
		10b-11b	Reserved
29-27 INITIALIZED_PO			Width of the ports after initialized (read only)
	RT_WIDTH
		000b	Single-lane port, lane 0
		001b	Single-lane port, lane 2
		010b	Four-lane port
		011b-	Reserved
		111b
26-24 PORT_WIDTH_O			Soft port configuration to override the hardware size
	VERRIDE
		000b	No override
		001b	Reserved
		010b	Force single lane, lane 0
		011b	Force single lane, lane 2
		100b-	Reserved
		111b
23	PORT_DISABLE		Port disable
		0b	Port receivers/drivers are enabled
		1b	Port receivers/drivers are disabled and are unable to receive/transmit to any packets or control
			symbols
22	OUTPUT_PORT_		Output port enable
	ENABLE
		0b	Port is stopped and not enabled to issue any packets except to route or respond to I/O logical
			MAINTENANCE packets, depending upon the functionality of the processing element. Control
			symbols are not affected and are sent normally.
		1b	Port is enabled to issue any packets
188	Serial RapidIO (SRIO)		SPRU976 –March 2006

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Texas Instruments TMS320C645x manual Port Control CSR n SPnCTL Field Descriptions

Contents

Users Guide Submit Documentation Feedback Contents Errrstevnticrr Base Device ID CSR Baseid List of Figures Load/Store Module Interrupt Condition Routing Registers 150 Port Error Rate Threshold CSR n SP n Errthresh List of Tables LSUn Control Register 0 LSUnREG0 Field Descriptions Base Device ID CSR Baseid Field Descriptions Read This First General RapidIO System RapidIO Architectural Hierarchy Overview RapidIO Interconnect Architecture 3 1x/4x LP-Serial RapidIO Feature Support in Srio Features Supported in Srio Features Not Supported StandardsExternal Devices Requirements RapidIO Documents and Links Overview Peripheral Data Flow Srio Packets Operation Sequence Operation Sequence Example Packet Streaming Write Control Symbols 4x RapidIO Packet Data Stream Streaming-Write Class Ftype Ttype Packet Type Srio Packet Ftype/TtypePacket Type Srio Pins Block DiagramFunctional Operation Pin Description Srio Conceptual Block Diagram Serdes and its Configurations Enabling the PLLBits of Serdescfg nCNTL Register 0x120 0x12c Bit Name Value Description Rate Bit Effects Bits of Serdescfg nCNTL Register 0x120 0x12cLine Rate versus PLL Output Clock Frequency Bits of Serdescfgrx nCNTL Registers Frequency Range versus MPYEnabling the Receiver Bit Field Value Description 1514 Disabled. Loss of signal detection disabledBits of SERDESCFGRXnCNTL Registers EQ Bits Enabling the TransmitterBits of Serdescfgtx nCNTL Registers CFGRX2219 Low Freq Gain DE Bits Bits of Serdescfgtx nCNTL RegistersSwing Bits Serdes Configuration Example DirectIO Control/Command Register Field Mapping RapidIO Packet Header Field Control/Command Register RapidIO Packet Header Field Status FieldsStatus Field Function BSY LSU Registers Timing Example Burst Nwriter Detailed Data Path Description TX Operation Write Transactions Read Transactions Segmentation RX Operation Reset and Power Down State Message Passing Cppi RX Scheme for RapidIO Queue Mapping Table Address Offset 0x0800 0x08FC Queue Mapping Register Rxumapl n Bit Name Description RX Buffer Descriptor Fields RX Buffer Descriptor Field Descriptions Field Description RX Buffer Descriptor Field Descriptions Field Description RX Cppi Mode Explanation Cppi Boundary Diagram TX Buffer Descriptor Fields TX Buffer Descriptor Field Definitions Uses this bit to reclaim buffers Ssize Name Bit Access Reset Value Description TXQUEUECNTL0- Address Offset 0x7E0TXQUEUECNTL1- Address Offset 0x7E4 TXQUEUECNTL2- Address Offset 0x7E8 TXQueueMap10 2316 0x0A Detailed Data Path Description TX Operation Message Passing Software RequirementsRX Operation RX Buffer Descriptor Initialization ExampleQueue Mapping TX Buffer Descriptor NDP Maintenance Start Message Passing Doorbell Doorbell Operation Congestion Control Detailed Description Name Bit Transmit Source Flow Control Masks Configuration Bus Example Endianness Reset DMA Example BLK8ENSTA BLK7ENSTA Reset SummaryEnable and Enable Status Registers Enable and Enable Status Bit Field Descriptions EnstatGblen BLK0EN BLK1EN BLK1ENSTATBLK2EN BLK2ENSTAT Software Shutdown Details EmulationBLK8ENSTAT Peren Soft Free Peren Emulation Control SignalsEnabling the Srio Peripherals Set Device ID Registers 11.2 PLL, Ports, Device ID and Data Rate InitializationsPeripheral Initializations Assert the Peren bit to enable logical layer data flow Read register to check portx1-4 OK bit Bootload Capability ConfigurationBootload Data Movement Device Wakeup MSG REQ ERR CPU Interrupts General Description Interrupt Condition Control Registers Interrupt Source Configuration Options Where ICS0 Doorbell1, bit 0, through ICS15 Doorbell1, bit Interrupt Conditions LSU Interrupt Condition Clear Registers Iccr Address Offset ICS11 ICS10 ICS9 ICS8 ICS2 ICS1 ICS0ICC11 ICC10 ICC9 ICC8 ICC2 ICC1 ICC0 Interrupt Condition Routing Options DOORBELL0ICRR2 Address Offset LSUICRR3 Address Offset 0x02EC LSUICRR1 Address Offset 0x02E4LSUICRR2 Address Offset 0x02E8 Interrupt Status Decode Registers ERRRSTEVNTICRR2 Address Offset 0x02F4ERRRSTEVNTICRR3 Address Offset 0x02F8 ICR2 ICR1 ICR0 Sharing of Isdr Bits ISDR3 ISDR2 ISDR1 ISDR9 ISDR8 ISDR7 ISDR6 ISDR5 ISDR4 ISDR0 Interrupt GenerationInterrupt Pacing Interrupt Handling INTDSTnRATECNTL Interrupt Rate Control Register Interrupt Conditions Offset Acronym Register Description IntroductionSerial Rapid IO Srio Registers Serial Rapid IO Srio Registers Offset Acronym Register Description LSUICRR3 ErrrstevnticRR2 RR3 LSU3REG1 QUEUE1TXDMAC QUEUE2TXDMACQUEUE3TXDMAC QUEUE4TXDMAC QUEUE12RXDMA Txcppiflowma SKS6SKS7 Rxqueuetear RXUMAPL18 RXUMAPH18RXUMAPL19 RXUMAPH19 Asblyid AsblyinfoPefeat Srcop SP0ERRATTRCA PTDBG0SP0ERRCAPTDB SP0ERRRATE Timer SP3ERRRATESP3ERRTHRESH Spipdiscovery Peripheral Identification Register PID Peripheral ID Register PID Field DescriptionsType Class REV Peripheral Control Register PCR Peripheral Control Register PCR Field DescriptionsPere Soft Free Bit Field Peripheral Settings Control Register Persetcntl Cbatranspr 1XMODEPrescalerse Lect ENPLL1 ENPLL3ENPLL2 Peripheral Global Enable Register Gblen Peripheral Global Enable Register Gblen Field Descriptions Peripheral Global Enable Status Register Gblenstat GBLENS TAT Block n Enable Register BLKnEN Block n Enable Register BLKnEN Field Descriptions Block n Enable Status Register BLKnENSTAT Block n Enable Status Register BLKnENSTAT RapidIO DEVICEID1 Register DEVICEIDREG1 RapidIO DEVICEID1 Register DEVICEIDREG1 Field Descriptions8BNODEID 16BNODEID RapidIO DEVICEID2 Register DEVICEIDREG2 RapidIO DEVICEID2 Register DEVICEIDREG2 Field Descriptions Packet Forwarding Register n for 16b DeviceIDs PF16BCNTLn Packet Forwarding Register n for 8b DeviceIDs PF8BCNTLn CDR LOS Align Term Invpa Rate Buswidth CFGRX2219 Low Freq Gain Zero Freq at e28 min Entx EnftSwing Invpa Rate Buswidth Swing Bits DE BitsCFGTX119 Amplitude mV dfpp CFGTX1512 Amplitude Reduction Serdes Macro Configuration Register n SERDESCFGnCNTL MPY EnpllRIOCLK/RIOCLK MPY DOORBELLn Interrupt Status Register DOORBELLnICSR DOORBELLn Interrupt Status Register DOORBELLnICSR DOORBELLn Interrupt Clear Register DOORBELLnICCR DOORBELLn Interrupt Clear Register DOORBELLnICCR RX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Status Register Rxcppiicsr RX Cppi Interrupt Clear Register Rxcppiiccr RX Cppi Interrupt Clear Register Rxcppiiccr TX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Status Register Txcppiicsr TX Cppi Interrupt Clear Register Txcppiiccr TX Cppi Interrupt Clear Register Txcppiiccr ICS31-0 Load/Store module interrupt condition status bits LSU Status Interrupt Register LsuicsrLSU Status Interrupt Register Lsuicsr Field Descriptions ICS31-0 Load/Store module interrupt clear bits LSU Clear Interrupt Register LSU IccrLSU Clear Interrupt Register LSU Iccr Field Descriptions 31-17 126 DOORBELLn Interrupt Condition Routing Register DOORBELLnICRR 128 RX Cppi Interrupt Condition Routing Register Rxcppi Icrr ICR RX Cppi Interrupt condition routing bits RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2 RX Cppi Interrupt Condition Routing Register Rxcppi ICRR2 TX Cppi Interrupt Condition Routing Register Txcppi Icrr ICR TX Cppi Interrupt condition routing bits TX Cppi Interrupt Condition Routing Register Txcppi ICRR2 TX Cppi Interrupt Condition Routing Register Txcppi ICRR2 LSU Module Interrupt Condition Routing Register 0 LSUICRR0 ICR LSU Module Interrupt Condition Routing Register 1 LSUICRR1 LSU Module Interrupt Condition Routing Register 1 LSUICRR1 LSU Module Interrupt Condition Routing Register 2 LSUICRR2 LSU Module Interrupt Condition Routing Register 2 LSUICRR2 LSU Module Interrupt Condition Routing Register 3 LSUICRR3 LSU Module Interrupt Condition Routing Register 3 LSUICRR3 Errrstevnticrr Errrstevnticrr Field Descriptions ERRRSTEVNTICRR2 Field Descriptions ICR11 ERRRSTEVNTICRR3 ERRRSTEVNTICRR3 Field Descriptions INTDSTn Interrupt Status Decode Registers INTDSTnDECODE INTDSTn Interrupt Status Decode Registers INTDSTnDECODE INTDSTn Interrupt Rate Control Registers INTDSTnRATECNTL CountdownvalueCountdown Value LSUn Control Register 0 LSUnREG0 LSU n Control Register 0 LSU nREG0 Field DescriptionsAddressmsb Bit Ext address fields Addresslsbconfigoffset Addresslsb Configoffse TLSUn Control Register 1 LSUnREG1 LSU n Control Register 1 LSU nREG1 Field Descriptions LSUn Control Register 2 LSUnREG2 LSU n Control Register 2 LSU nREG2 Field DescriptionsDspaddress 32b DSP byte address Bytecount LSUn Control Register 3 LSUnREG3LSU n Control Register 3 LSU nREG3 Field Descriptions LSUn Control Register 4 LSUnREG4 LSUn Control Register 4 LSUnREG4 Field Descriptions LSUn Control Register 5 LSUnREG5 LSU n Control Register 5 LSU nREG5 Field DescriptionsDrbllinfo Hopcount Packettype LSUn Control Register 6 LSUnREG6 LSUn Control Register 6 LSUnREG6 Field DescriptionsCompletioncode BSY Completionc LSU Congestion Control Flow Mask n Lsuflowmasks n Flowmask Txhdp Txcp Rxhdp Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP Queue Receive DMA Completion Pointer Registers QUEUEnRXDMACP Transmit Queue Teardown Register Txqueueteardown QUEUE1FLOWMASK QUEUE0FLOWMASK QUEUE3FLOWMASK QUEUE2FLOWMASKQUEUE5FLOWMASK QUEUE4FLOWMASK QUEUE7FLOWMASK QUEUE6FLOWMASK QUEUE15FLOWMASK QUEUE14FLOWMASK Mask Receive Queue Teardown Register Rxqueueteardown Receive Queue Teardown Register Rxqueueteardown Receive Cppi Control Register Rxcppicntl Receive Cppi Control Register Rxcppicntl Field Descriptions Txqueuemap 3NUMMSGS3QUEUEPTR 2NUMMSGS 7NUMMSGS 7QUEUEPTR6NUMMSGS 6QUEUEPTR 11NUMMSGS 11QUEUEPTR10NUMMSGS 10QUEUEPTR 15NUMMSGS 15QUEUEPTR14NUMMSGS 14QUEUEPTR Mailbox-to-Queue Mapping Register Ln RXUMAPLn Mailbox-to-Queue Mapping Register Hn RXUMAPHn Flow Control Table Entry Registers FLOWCNTLn Flowcntlid Device Identity CAR Devid Device Identity CAR Devid Field Descriptions Device Information CAR Devinfo Device Information CAR Devinfo Field DescriptionsDevicerev Vendor supply device revision Assembly Identity CAR Asblyid Assembly Identity CAR Asblyid Field Descriptions Assembly Information CAR Asblyinfo Assembly Information CAR Asblyinfo Field Descriptions Processing Element Features CAR Pefeat Processing Element Features CAR Pefeat Field Descriptions Source Operations CAR Srcop Source Operations CAR Srcop Field Descriptions Destination Operations CAR Destop Destination Operations CAR Destop Field Descriptions Processing Element Logical Layer Control CSR Pellctl ExtendedaddressIngcontrol Ressingcont Local Configuration Space Base Address 0 CSR Lclcfghbar Lcsba Local Configuration Space Base Address 1 CSR Lclcfgbar Local Configuration Space Base Address 1 CSR Lclcfgbar Base Device ID CSR Baseid Base Device ID CSR Baseid Field Descriptions Host Base Device ID Lock CSR Hostbaseidlock HostbasedeviceidHostbasede Viceid Componenttag Component Tag CSR ComptagComponent Tag CSR Comptag Field Descriptions Efptr Efid Port Link Timeout Control CSR Spltctl Field Descriptions Port Link Time-Out Control CSR Spltctl Port Response Time-Out Control CSR Sprtctl Port Response Time-Out Control CSR Sprtctl Port General Control CSR Spgenctl Port General Control CSR Spgenctl Field Descriptions Port Link Maintenance Request CSR n SPnLMREQ Command Port Link Maintenance Response CSR n SPnLMRESP Port Local AckID Status CSR n SPnACKIDSTAT Port Error and Status CSR n SPnERRSTAT Port Error and Status CSR n SPnERRSTAT Field Descriptions Lized PortokPortuninitia Port Control CSR n SPnCTL Port Control CSR n SPnCTL Field Descriptions Port Control CSR n SP nCTL Field Descriptions Nable Error Reporting Block Header Errrptbh Error Reporting Block Header Errrptbh Field Descriptions Logical/Transport Layer Error Detect CSR Errdet Logical/Transport Layer Error Enable CSR Erren 50 bit addresses Logical/Transport Layer High Address Capture CSR HaddrcaptADDRESS6332 Xamsbs Logical/Transport Layer Address Capture CSR AddrcaptADDRESS313 Logical/Transport Layer Device ID Capture CSR Idcapt Msbdestid DestidMsbsourceid Sourceid Msbdestid Logical/Transport Layer Control Capture CSR Ctrlcapt Ftype Ttype MsginfoImpspecific Ftype Port-Write Target Device ID CSR Pwtgtid Port-Write Target Device ID CSR Pwtgtid Field DescriptionsDeviceidmsb Deviceid Port Error Detect CSR n SPnERRDET Port Error Detect CSR n SPnERRDET Field Descriptions Port Error Rate Enable CSR n SPnRATEEN Port Error Rate Enable CSR n SPnRATEEN Field Descriptions Port n Attributes Error Capture CSR 0 SPnERRATTRCAPTDBG0 CAPTURE0 CAPTURE0 CAPTURE1 CAPTURE1 CAPTURE2 CAPTURE2 CAPTURE3 CAPTURE3 Port Error Rate CSR n SPnERRRATE Port Error Rate CSR n SPnERRRATE Field Descriptions Port Error Rate Threshold CSR n SPnERRTHRESH Port IP Discovery Timer in 4x mode Spipdiscoverytimer DiscoverytimerPwtimer Discoveryti Port IP Mode CSR Spipmode Port IP Mode CSR Spipmode Field Descriptions Port IP Mode CSR Spipmode Field Descriptions Rsten Prescale Serial Port IP Prescalar IpprescalSerial Port IP Prescalar Ipprescal Field Descriptions Port-Write-In Capture CSR n SPIPPWINCAPTn Pwcapt Portid Port Reset Option CSR n SPnRSTOPTPort Reset Option CSR n SP nRSTOPT Field Descriptions Port Control Independent Register n SPnCTLINDEP Maxretryen MaxretryerMaxretryth Irqen Silencetimer Port Silence Timer n SPnSILENCETIMERPort Silence Timer n SPnSILENCETIMER Field Descriptions Multevntcs Multevntcs Port Control Symbol Transmit n SPnCSTX Port Control Symbol Transmit n SP nCSTX Field Descriptions Important Notice