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SRIO Registers
5.85Port Control CSR n (SPn_CTL)
Each of the four ports is supported by a register of this type.
Figure 141. Port Control CSR n (SPn_CTL)
23 | 22 | 21 | 20 | 19 |
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PORT_WIDTH INITIALIZED_PORT_WI PORT_WIDTH_OVERRI PORT OUTP | INPUT | ERRO | MULTI |
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| DTH | DE | _DISA | UT_P | _POR R_CH | CAST |
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| BLE | ORT_ | T_EN ECK_ _PAR |
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| ENAB | ABLE | DISAB | TICIP |
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| LE |
| LE | ANT |
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RW- | RW- | RW- | RW- | RW- |
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| 0x00 | 0x00 | 0x00 | 0x00 | 0x00 |
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LEGEND: R = Read only; |
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| 3 | 2 | 1 | 0 | |
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| Reserved |
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| STOP | DROP | PORT | PORT |
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| _POR | _PAC | _LOC | _TYPE |
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| T_FLD KET_E KOUT |
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| _ENC | NABL |
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| _ENA | E |
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| BLE |
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| RW- | RW- | RW- | R- | |
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| 0x00 | 0x00 | 0x00 | 0x01 |
LEGEND: R = Read only;
Table 115. Port Control CSR n (SPn_CTL) Field Descriptions
Bit | Field | Value | Description |
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| Hardware width of the port (read only). Only 00b is valid for SP1, SP2, and SP3 | |
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| 00b | |
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| 01b | |
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| Reserved | |
| Width of the ports after initialized (read only) | ||
| RT_WIDTH |
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| 000b | |
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| 001b | |
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| 010b | |
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| 011b- | Reserved |
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| 111b |
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| Soft port configuration to override the hardware size | ||
| VERRIDE |
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| 000b | No override |
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| 001b | Reserved |
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| 010b | Force single lane, lane 0 |
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| 011b | Force single lane, lane 2 |
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| 100b- | Reserved |
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| 111b |
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23 | PORT_DISABLE |
| Port disable |
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| 0b | Port receivers/drivers are enabled |
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| 1b | Port receivers/drivers are disabled and are unable to receive/transmit to any packets or control |
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22 | OUTPUT_PORT_ |
| Output port enable |
| ENABLE |
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| 0b | Port is stopped and not enabled to issue any packets except to route or respond to I/O logical |
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| MAINTENANCE packets, depending upon the functionality of the processing element. Control |
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| symbols are not affected and are sent normally. |
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| 1b | Port is enabled to issue any packets |
188 | Serial RapidIO (SRIO) |
| SPRU976 |
