Texas Instruments TMS320C645x Status Fields, Control/Command Register RapidIO Packet Header Field

www.ti.com

SRIO Functional Description

Table 13. Control/Command Register Field Mapping (continued)

Control/Command Register	RapidIO Packet Header Field
Field
Packet Type	4 msb = 4b ftype field for all packets and
	4 lsb = 4b trans field for packet types 2,5,8.
OutPortID	Not available in RapidIO header.
	Indicates the output port number for the packet to be transmitted from. Specified by the CPU
	along with NodeID.
Drbll Info	RapidIO doorbell info field for type 10 packets.
Hop Count	RapidIO hop_count field specified for Type 8 Maintenance packets.
Interrupt Req	Not available in RapidIO header.
	CPU controlled request bit used for interrupt generation. Typically used in conjunction with
	non-posted commands to alert the CPU when the requested data/status is present.
	0b - An interrupt is not requested upon completion of command
	1b- An interrupt is requested upon completion of command

		Table 14. Status Fields
Status Field	Function
BSY	Indicates status of the command registers.
	0b - Command registers are available (writable) for next set of transfer descriptors
	1b - Command registers are busy with current transfer
Completion Code	Indicates the status of the pending command.
	000b	– Transaction complete, no errors (Posted/Non-posted)
	001b	– Transaction timeout occurred on Non-posted transaction
	010b	– Transaction complete, packet not sent due to flow control blockade (Xoff)
	011b	– Transaction complete, non-posted response packet (type 8 and 13) contained ERROR status, or
	response payload length was in error
	100b	– Transaction complete, packet not sent due to unsupported transaction type or invalid programming
	encoding for one or more LSU register fields
	101b	– DMA data transfer error
	110b	– Retry DOORBELL response received, or Atomic Test-and-swap was not allowed (semaphore in
	use)
	111b	– Transaction complete, packet not sent due to unavailable outbound credit at given priority (1)

(1)Status available only when Bsy signal = 0.

Four LSU register sets exist. This allows four outstanding requests for all transaction types that require a response (i.e., non-posted). For multi-core devices, software manages the usage of the registers. A shared configuration bus accesses all register sets. A single core device can utilize all four LSU blocks.

Figure 11 shows the timing diagram for accessing the LSU registers. Bsy signal is deasserted. LSU_Reg1 is written on configuration bus clock cycle T0, LSU_Reg2 is written on cycle T1, LSU_Reg3 is written on cycle T2, LSU_Reg4 is written on cycle T3. The command register LSU_Reg5 is written on cycle T4. The extended address field in LSU_Reg0 is assumed to be constant in this example. Upon completion of the write to the command register (next clock cycle T5), the Bsy signal is asserted, at which point the preceding completion code is invalid and accesses to the LSU registers are not allowed. Once the transaction completes (either as a successful transmission, or unsuccessfully, such as flow control prevention or response timeout) and any required interrupt service routine is completed, the Bsy signal is deasserted and the completion code becomes valid and the registers are accessible again.

34 Serial RapidIO (SRIO) SPRU976 –March 2006

Submit Documentation Feedback