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SRIO Registers
5.27DOORBELLn Interrupt Condition Routing Register 2 (DOORBELLn_ICRR2)
Each of the four doorbells is supported by a register of this type.
Figure 83. DOORBELLn Interrupt Condition Routing Register 2 (DOORBELLn_ICRR2)
31 | 28 | 27 | 24 | 23 | 20 | 19 | 16 |
ICR15 |
| ICR14 |
| ICR13 |
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| ICR12 |
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15 | 12 | 11 | 8 | 7 | 4 | 3 | 0 |
ICR11 |
| ICR10 |
| ICR9 |
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| ICR8 |
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LEGEND: R = Read, W = Write, n = value at reset |
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| Table 57. DOORBELLn Interrupt Condition Routing Register 2 (DOORBELLn_ICRR2) Field | |
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| Descriptions |
Bit | Field | Value Description |
ICR | Doorbell n (0 to 3) CPU servicing interrupt condition routing bits |
128 | Serial RapidIO (SRIO) | SPRU976 |
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